Study of the performance of fault-tolerant multi-level inverter included in shunt active power filter

Nowadays, the large number of shunt active power filters (SAPF) is installed in many grid networks to eliminate the source currents harmonics and enhance power quality. These filters are installed in different places according to the filtration requirements. The connection between SAPF and grid network has a negative effect during the open-circuit fault of the insulated gate bipolar transistor (IGBT) switch of the SAPF. This paper proposes the application of the new diagnostic method based on the trigonometric circle and mean value variations techniques to the early detection and precise location of the open-circuit fault of the IGBT switches, and the inclusion of the modified reconfigurable inverter topology to allow the perfect continuity of the filter currents, and improve the diagnostic of the open-circuit fault. A single-sided amplitude spectrum technique (SSAS) is applied on the source currents to get the THDi% value. The obtained simulation results prove, the great success of the proposed diagnostic method, the ability of the modified reconfigurable inverter to be adapted to the grid network, the short response time between the diagnosis and the reconfiguration process is about 7 ms which is very sufficient to guarantee the rapid continuity of the shunt active power filter

Fault Tolerant DC–DC Converters at Homes and Offices

The emergence of direct current (DC) microgrids within the context of residential buildings and offices brings in a whole new paradigm in energy distribution. As a result, a set of technical challenges arise, concerning the adoption of efficient, cost-effective, and reliable DC-compatible power conditioning solutions, suitable to interface DC microgrids and energy consuming elements. This thesis encompasses the development of DC–DC power conversion solutions, featuring improved availability and efficiency, suitable to meet the requirements of a comprehensive set of end-uses commonly found in homes and offices. Based on the energy consumption profiles and requirements of the typical elements found at homes and offices, three distinctive groups are established: light-emitting diode (LED) lighting, electric vehicle (EV) charging, and general appliances. For each group, a careful evaluation of the criteria to fulfil is performed, based on which at least one DC–DC power converter is selected and investigated. Totally, a set of five DC–DC converter topologies are addressed in this work, being specific aspects related to fault diagnosis and/or fault tolerance analysed with particular detail in two of them. Firstly, mathematical models are described for LED devices and EV batteries, for the development of a theoretical analysis of the systems’ operation through computational simulations. Based on a compilation of requirements to account for in each end-use (LED lighting, EV charging, and general appliances), brief design considerations are drawn for each converter topology, regarding their architecture and control strategy. Aiming a detailed understanding of the two DC–DC power conversion systems subjected to thorough evaluation in this work – interleaved boost converter and fault-tolerant single-inductor multiple-output (SIMO) converter – under both normal and abnormal conditions, the operation of the systems is evaluated in the presence of open-circuit (OC) faults. Parameters of interest are monitored and evaluated to understand how the failures impact the operation of the entire system. At this stage, valuable information is obtained for the development of fault diagnosis strategies. Taking profit of the data collected in the analysis, a novel fault diagnostic strategy is presented, targeting interleaved DC–DC boost converters for general appliances. Ease of implementation, fast diagnostic and robustness against false alarms distinguish the proposed approach over the state-of-the-art. Its effectiveness is confirmed through a set of operation scenarios, implemented in both simulation environment and experimental context. Finally, an extensive set of reconfiguration strategies is presented and evaluated, aiming to grant fault tolerance capability to the multiple DC–DC converter topologies under analysis. A hybrid reconfiguration approach is developed for the interleaved boost converter. It is demonstrated that the combination of reconfiguration strategies promotes remarkable improvements on the post-fault operation of the converter. In addition, an alternative SIMO converter architecture, featuring inherent tolerance against OC faults, is presented and described. To exploit the OC fault tolerance capability of the fault-tolerant SIMO converter, a converter topology targeted at residential LED lighting systems, two alternative reconfiguration strategies are presented and evaluated in detail. Results obtained from computational simulations and experimental tests confirm the effectiveness of the approaches. To further improve the fault-tolerant SIMO converter with regards to its robustness against sensor faults, while simplifying its hardware architecture, a sensorless current control strategy is presented. The proposed control strategy is evaluated resorting to computational simulations.O surgimento de micro-redes em corrente contínua (CC) em edifícios residenciais e de escritórios estabelece um novo paradigma no domínio da distribuição de energia. Como consequência disso, surge uma panóplia de desafios técnicos ligados à adopção de soluções de conversão de energia, compatíveis com CC, que demonstrem ser eficientes, rentáveis e fiáveis, capazes de estabelecer a interface entre micro-redes em CC e as cargas alimentadas por esse sistema de energia. Até aos dias de hoje, os conversores CC–CC têm vindo a ser maioritariamente utilizados em aplicações de nicho, que geralmente envolvem níveis de potência reduzidos. Porém, as perspectivas futuras apontam para a adopção, em larga escala, destas tecnologias de conversão de energia, também em equipamentos eléctricos residenciais e de escritórios. Tal como qualquer outra tecnologia de conversão electrónica de potência, os conversores CC–CC podem ver o seu funcionamento afectado por falhas que degradam o seu bom funcionamento, sendo que essas falhas acabam por afectar não apenas os conversores em si, mas também as cargas que alimentam, limitando assim o tempo de vida útil do conjunto conversor + carga. Desta forma, é fulcral localizar a origem da falha, para que possam ser adoptadas acções correctivas, capazes de limitar as consequências nefastas associadas à falha. Para responder a este desafio, esta tese contempla o desenvolvimento de soluções de conversão de energia CC–CC altamente eficientes e fiáveis, capazes de responder a requisitos impostos por um conjunto alargado de equipamentos frequentemente encontrados em habitações e escritórios. Com base nos perfis de consumo de energia eléctrica e nos requisitos impostos pelas cargas tipicamente utilizadas em habitações e escritórios, são estabelecidos três grupos distintos: iluminação através de díodos emissores de luz, carregamento de veículo eléctrico (VE) e aparelhos eléctricos em geral. Para cada grupo, é efectuada uma avaliação cuidadosa dos critérios a respeitar, sendo com base nesses critérios que será escolhida e investigada pelo menos uma topologia de conversor CC–CC. No total, são abordadas cinco topologias de conversores CC–CC distintas, sendo que os aspectos ligados ao diagnóstico de avarias e/ou tolerância a falhas são analisados com particular detalhe em duas dessas topologias. Inicialmente, são estabelecidos modelos matemáticos descritivos do comportamento das principais cargas consideradas no estudo – díodos emissores de luz e baterias de VEs – visando a análise teórica do funcionamento dos sistemas em estudo, suportada por simulações computacionais. Com base numa compilação de requisitos a ter em conta em cada aplicação – iluminação através de díodos emissores de luz, carregamento de veículo eléctrico (VE) e aparelhos eléctricos em geral – são estabelecidas considerações ligadas à escolha de cada topologia de conversor não isolado, no que respeita à sua arquitectura e estratégia de controlo. Visando o conhecimento aprofundado das duas topologias de conversor CC–CC alvo de particular enfoque neste trabalho – conversor entrelaçado elevador e conversor de entrada única e múltiplas saídas, tolerante a falhas – quer em funcionamento normal, quer em funcionamento em modo de falha, é avaliado o funcionamento de ambas as topologias na presença de falhas de circuito aberto nos semicondutores activos. Para o efeito, são monitorizados e analisados parâmetros úteis à percepção da forma como os modos de falha avaliados neste trabalho impactam o funcionamento de todo o sistema. Nesta fase, é obtida informação fundamental ao desenvolvimento de estratégias de diagnóstico de avarias, particularmente indicadas para avarias de circuito aberto nos semicondutores activos dos conversores em estudo. Com base na informação recolhida anteriormente, é apresentada uma nova estratégia de diagnóstico de avarias direccionada a conversores CC–CC elevadores entrelaçados utilizados em aparelhos eléctricos, em geral. Facilidade de implementação, rapidez e robustez contra falsos positivos são algumas das características que distinguem a estratégia proposta em relação ao estado da arte. A sua efectividade é confirmada com recurso a uma multiplicidade de cenários de funcionamento, implementados quer em ambiente de simulação, quer em contexto experimental. Por fim, é apresentada e avaliada uma gama alargada de estratégias de reconfiguração, que visam assegurar a tolerância a falhas das diversas topologias de conversores CC–CC em estudo. É desenvolvida uma estratégia de reconfiguração híbrida, direccionada ao conversor entrelaçado elevador, que combina múltiplas medidas de reconfiguração mais simples num único procedimento. Demonstra-se que a combinação de múltiplas estratégias de reconfiguração introduz melhorias substanciais no funcionamento do conversor ao longo do período pós-falha, ao mesmo tempo que assegura a manutenção da qualidade da energia à entrada e saída do conversor reconfigurado. Noutra frente, é apresentada e descrita uma arquitectura alternativa do conversor de entrada única e múltiplas saídas, com tolerância a falhas de circuito aberto. Através da configuração proposta, é possível manter o fornecimento de energia eléctrica a todas as saídas do conversor. Para tirar máximo proveito da tolerância a falhas do conversor de entrada única e múltiplas saídas, uma topologia de conversor indicada para sistemas residenciais de iluminação baseados em díodos emissores de luz, são apresentadas e avaliadas duas estratégias de reconfiguração do conversor, exclusivamente baseadas na adaptação do controlo aplicado ao conversor. Os resultados de simulação computacional e os resultados experimentais obtidos confirmam a efectividade das abordagens adoptadas, através da melhoria da qualidade da energia eléctrica fornecida às diversas saídas do conversor. São assim asseguradas condições essenciais ao funcionamento ininterrupto e estável dos sistemas de iluminação, já que a qualidade da energia eléctrica fornecida aos sistemas de iluminação tem impacto directo na qualidade da luz produzida. Por fim, e para aprimorar o conversor de entrada única e múltiplas saídas tolerante a falhas, no que respeita à sua robustez contra falhas em sensores, é apresentada uma estratégia de controlo de corrente que evita o recurso excessivo a sensores e, ao mesmo tempo, simplifica a estrutura de controlo do conversor. A estratégia apresentada é avaliada através de simulações computacionais. A abordagem apresentada assume vantagens em múltiplos domínios, sendo de destacar vantagens como a melhoria da fiabilidade de todo o sistema de iluminação (conversor + carga), os ganhos atingidos ao nível do rendimento, a redução do custo de implementação da solução, ou a simplificação da estrutura de controlo.This work was supported by the Portuguese Foundation for Science and Technology (FCT) under grant number SFRH/BD/131002/2017, co-funded by the Ministry of Science, Technology and Higher Education (MCTES), by the European Social Fund (FSE) through the ‘Programa Operacional Regional Centro’ (POR-Centro), and by the Human Capital Operational Programme (POCH)

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levelsSiirretty Doriast

Parallel Architectures for Planetary Exploration Requirements (PAPER)

The Parallel Architectures for Planetary Exploration Requirements (PAPER) project is essentially research oriented towards technology insertion issues for NASA's unmanned planetary probes. It was initiated to complement and augment the long-term efforts for space exploration with particular reference to NASA/LaRC's (NASA Langley Research Center) research needs for planetary exploration missions of the mid and late 1990s. The requirements for space missions as given in the somewhat dated Advanced Information Processing Systems (AIPS) requirements document are contrasted with the new requirements from JPL/Caltech involving sensor data capture and scene analysis. It is shown that more stringent requirements have arisen as a result of technological advancements. Two possible architectures, the AIPS Proof of Concept (POC) configuration and the MAX Fault-tolerant dataflow multiprocessor, were evaluated. The main observation was that the AIPS design is biased towards fault tolerance and may not be an ideal architecture for planetary and deep space probes due to high cost and complexity. The MAX concepts appears to be a promising candidate, except that more detailed information is required. The feasibility for adding neural computation capability to this architecture needs to be studied. Key impact issues for architectural design of computing systems meant for planetary missions were also identified

Contribution of the two rectifiers reconfiguration to fault tolerance connected to the grid network to feed the GMAW through processor-in-the-loop

This study aims to propose a new diagnosis technique based on the Park’s vector and the polar coordinates of electric currents for the detection and location of open-circuit faults (OC) at the level of two rectifiers connected to the grid network to feed the Gas Metal Arc Welding process (GMAW). This diagnosis technique allows the early location of faulty switches (Thyristors) to overcome the negative effect of faulty rectifiers on welding current, welding voltage, and droplet diameter. For that, the reconfigurable rectifiers have been integrated to accomplish the welding process. The proposed diagnosis technique is applied to reconfigurable rectifiers connected to the GMAW system through numerical simulations using MATLAB/Simulink and real-time processor-in-the-loop (PIL) implementation via DSpace ds 1103 card. The simulation and PIL experimental results show similar trends and great success of the diagnosis technique and the two rectifiers reconfiguration for overcoming the open circuit faults and obtaining high welding quality while maintaining the work-piece and avoiding the distortions caused by the faulty rectifiers, which affecting the grid network and on the GMAW system at the same time

Reliability and fault tolerance modelling of multiprocessor systems

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Reliability evaluation by analytic modelling constitute an important issue of designing a reliable multiprocessor system. In this thesis, a model for reliability and fault tolerance analysis of the interconnection network is presented, based on graph theory. Reliability and fault tolerance are considered as deterministic and probabilistic measures of connectivity. Exact techniques for reliability evaluation fail for large multiprocessor systems because of the enormous computational resources required. Therefore, approximation techniques have to be used. Three approaches are proposed, the first by simplifying the symbolic expression of reliability; the other two by applying a hierarchical decomposition to the system. All these methods give results close to those obtained by exact techniques.Consejo Nacional de Ciencia y Tecnologia" (National Council for Science and Technology of Mexico) and "Instituto de Investigaciones Electricas" (Institute for Electrical Research

On Dynamic Monitoring Methods for Networks-on-Chip

Rapid ongoing evolution of multiprocessors will lead to systems with hundreds of processing cores integrated in a single chip. An emerging challenge is the implementation of reliable and efficient interconnection between these cores as well as other components in the systems. Network-on-Chip is an interconnection approach which is intended to solve the performance bottleneck caused by traditional, poorly scalable communication structures such as buses. However, a large on-chip network involves issues related to congestion problems and system control, for instance. Additionally, faults can cause problems in multiprocessor systems. These faults can be transient faults, permanent manufacturing faults, or they can appear due to aging. To solve the emerging traffic management, controllability issues and to maintain system operation regardless of faults a monitoring system is needed. The monitoring system should be dynamically applicable to various purposes and it should fully cover the system under observation. In a large multiprocessor the distances between components can be relatively long. Therefore, the system should be designed so that the amount of energy-inefficient long-distance communication is minimized. This thesis presents a dynamically clustered distributed monitoring structure. The monitoring is distributed so that no centralized control is required for basic tasks such as traffic management and task mapping. To enable extensive analysis of different Network-on-Chip architectures, an in-house SystemC based simulation environment was implemented. It allows transaction level analysis without time consuming circuit level implementations during early design phases of novel architectures and features. The presented analysis shows that the dynamically clustered monitoring structure can be efficiently utilized for traffic management in faulty and congested Network-on-Chip-based multiprocessor systems. The monitoring structure can be also successfully applied for task mapping purposes. Furthermore, the analysis shows that the presented in-house simulation environment is flexible and practical tool for extensive Network-on-Chip architecture analysis.Siirretty Doriast

Fault Diagnosis and Reconfiguration of Multilevel Inverter Switch Failure-A Performance Perspective

Multilevel Inverters (MLI) gains importance in Distribution systems, Electrical Drive systems, HVDC systems and many more applications. As Multilevel Inverters comprises of number of power switches the fault diagnosis of MLI becomes tedious. This paper is an attempt to develop and analyze the fault diagnosis method that utilizes Artificial Neural Network to get it trained with the fault situations. A performance analysis of Genetic Algorithm (GA) and the Modified Genetic Algorithm (MGA), which optimizes the Artificial Neural Network (ANN) that trains itself on the fault detection, and reconfiguration of the Cascaded Multilevel Inverters (CMLI) is attempted. The Total Harmonic Distortion (THD) occurring due to switch failures or driver failures occurring in the CMLI is considered for this comparative analysis. Elapsed time of recovery, Mean Square Error (MSE) and the computational budgets of ANN are the performance parameters considered in this comparative analysis. Optimization is involved in the process of updating the weight and the bias values in the ANN network.  Matlab based simulation is carried out and the results are obtained and tabulated for the performance evaluation. It was observed that Modified Genetic Algorithm performed better than the Genetic Algorithm while optimizing the ANN training

Research and development of diagnostic algorithms to support fault accommodating control for emerging shipboard power system architectures

The U.S. Navy has proposed development of next generation warships utilising an increased amount of power electronics devices to improve flexibility and controllability. The high power density finite inertia network is envisioned to employ automated fault detection and diagnosis to aid timely remedial action. Integration of condition monitoring and fault diagnosis to form an intelligent power distribution system is anticipated to assist decision support for crew while enhancing security and mission availability. This broad research being in the conceptual stage has lack of benchmark systems to learn from. Thorough studies are required to successfully enable realising benefits offered by using increased power electronics and automation. Application of fundamental analysis techniques is necessary to meticulously understand dynamics of a novel system and familiarisation with associated risks and their effects. Additionally, it is vital to find ways of mitigating effects of identified risks. This thesis details the developing of a generalised methodology to help focus research into artificial intelligence (AI) based diagnostic techniques. Failure Mode and Effects Analysis (FMEA) is used in identifying critical parts of the architecture. Sneak Circuit Analysis (SCA) is modified to provide signals that differentiate faults at a component level of a dc-dc step down converter. These reliability analysis techniques combined with an appropriate AI-algorithm offer a potentially robust approach that can potentially be utilised for diagnosing faults within power electronic equipment anticipated to be used onboard the novel SPS. The proposed systematic methodology could be extended to other types of power electronic converters, as well as distinguishing subsystem level faults. The combination of FMEA, SCA with AI could also be used for providing enhanced decision support. This forms part of future research in this specific arena demonstrating the positives brought about by combining reliability analyses techniques with AI for next generation naval SPS.The U.S. Navy has proposed development of next generation warships utilising an increased amount of power electronics devices to improve flexibility and controllability. The high power density finite inertia network is envisioned to employ automated fault detection and diagnosis to aid timely remedial action. Integration of condition monitoring and fault diagnosis to form an intelligent power distribution system is anticipated to assist decision support for crew while enhancing security and mission availability. This broad research being in the conceptual stage has lack of benchmark systems to learn from. Thorough studies are required to successfully enable realising benefits offered by using increased power electronics and automation. Application of fundamental analysis techniques is necessary to meticulously understand dynamics of a novel system and familiarisation with associated risks and their effects. Additionally, it is vital to find ways of mitigating effects of identified risks. This thesis details the developing of a generalised methodology to help focus research into artificial intelligence (AI) based diagnostic techniques. Failure Mode and Effects Analysis (FMEA) is used in identifying critical parts of the architecture. Sneak Circuit Analysis (SCA) is modified to provide signals that differentiate faults at a component level of a dc-dc step down converter. These reliability analysis techniques combined with an appropriate AI-algorithm offer a potentially robust approach that can potentially be utilised for diagnosing faults within power electronic equipment anticipated to be used onboard the novel SPS. The proposed systematic methodology could be extended to other types of power electronic converters, as well as distinguishing subsystem level faults. The combination of FMEA, SCA with AI could also be used for providing enhanced decision support. This forms part of future research in this specific arena demonstrating the positives brought about by combining reliability analyses techniques with AI for next generation naval SPS

Methodologies for the Evaluation and Mitigation of Distribution Network Risk

Security of supply to customers is a major concern for electricity distribution network operators. This research concentrates in particular on the UK distribution system, and on sub-transmission and extra high voltage networks within that system. It seeks first to understand the principal causes of network risk and consequent loss of supply to customers as a result of faults at these voltage levels. It then develops a suite of methodologies to evaluate that risk, in terms of expected annual cost to the network operator, under a range of different scenarios and for both simple and complex network topologies. The scenarios considered include asset ageing, network automation and increasing utilisation as a consequence of electric vehicles and heat pumps. The methodologies also evaluate possible mitigation options, including active network management, and capital expenditure for both asset replacement and network reinforcement. A composite methodology is also developed, to consider combinations of scenarios and combinations of mitigation strategies. The thesis concludes by considering issues likely to affect the extent and possible increase of network risk over the period 2010-2030