2,503 research outputs found
Modelling Heterogeneous DSPâFPGA Based System Partitioning with Extensions to the Spinach Simulation Environment
In this paper we present system-on-a-chip extensions to the Spinach simulation environment for rapidly prototyping heterogeneous DSP/FPGA based architectures, specifically in the embedded domain. This infrastructure has been successfully
used to model systems varying from multiprocessor gigabit ethernet controllers to Texas Instruments C6x series DSP based systems with tightly coupled FPGA based coprocessors for computational offloading. As an illustrative example of this toolsets functionality, we investigate workload partitioning in heterogeneous
DSP/FPGA based embedded environments. Specifically, we focus on computational offloading of matrix multiplication kernels across DSP/FPGA based embedded architectures
Multimedia terminal system-on-chip design and simulation
This paper proposes a design approach based on integrated architectural and system-on-chip (SoC) simulations. The main idea is to have an efficient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW) digital signal processors (DSPs), the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA) simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
The design of MultiProcessor Systems-on-Chip
(MPSoC) emphasizes intellectual-property (IP)-based
communication-centric approaches. Therefore, for the optimization
of the MPSoC interconnect, the designer must develop
traffic models that realistically capture the application behavior
as executing on the IP core. In this paper, we introduce a
Reactive IP Emulator (RIPE) that enables an effective emulation
of the IP-core behavior in multiple environments, including bitand
cycle-true simulation. The RIPE is built as a multithreaded
abstract instruction-set processor, and it can generate reactive
traffic patterns. We compare the RIPE models with cycle-true
functional simulation of complex application behavior (tasksynchronization,
multitasking, and input/output operations).
Our results demonstrate high-accuracy and significant speedups.
Furthermore, via a case study, we show the potential use of the
RIPE in a design-space-exploration context
GPU accelerated Monte Carlo simulation of Brownian motors dynamics with CUDA
This work presents an updated and extended guide on methods of a proper
acceleration of the Monte Carlo integration of stochastic differential
equations with the commonly available NVIDIA Graphics Processing Units using
the CUDA programming environment. We outline the general aspects of the
scientific computing on graphics cards and demonstrate them with two models of
a well known phenomenon of the noise induced transport of Brownian motors in
periodic structures. As a source of fluctuations in the considered systems we
selected the three most commonly occurring noises: the Gaussian white noise,
the white Poissonian noise and the dichotomous process also known as a random
telegraph signal. The detailed discussion on various aspects of the applied
numerical schemes is also presented. The measured speedup can be of the
astonishing order of about 3000 when compared to a typical CPU. This number
significantly expands the range of problems solvable by use of stochastic
simulations, allowing even an interactive research in some cases.Comment: 21 pages, 5 figures; Comput. Phys. Commun., accepted, 201
An Adaptive Design Methodology for Reduction of Product Development Risk
Embedded systems interaction with environment inherently complicates
understanding of requirements and their correct implementation. However,
product uncertainty is highest during early stages of development. Design
verification is an essential step in the development of any system, especially
for Embedded System. This paper introduces a novel adaptive design methodology,
which incorporates step-wise prototyping and verification. With each adaptive
step product-realization level is enhanced while decreasing the level of
product uncertainty, thereby reducing the overall costs. The back-bone of this
frame-work is the development of Domain Specific Operational (DOP) Model and
the associated Verification Instrumentation for Test and Evaluation, developed
based on the DOP model. Together they generate functionally valid test-sequence
for carrying out prototype evaluation. With the help of a case study 'Multimode
Detection Subsystem' the application of this method is sketched. The design
methodologies can be compared by defining and computing a generic performance
criterion like Average design-cycle Risk. For the case study, by computing
Average design-cycle Risk, it is shown that the adaptive method reduces the
product development risk for a small increase in the total design cycle time.Comment: 21 pages, 9 figure
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