Analog I/Q FIR filter in 55-nm SiGe BiCMOS for 16-QAM optical communications at 112 Gb/s

We propose a novel implementation of a complex analog equalization filter for the compensation of frequency-dependent variations in coherent optical links. The analog compensation filter can be used in coherent-lite optical communication links where digital signal processing (DSP) is removed to limit the complexity and power consumption. In these links, the filter can compensate for electrical bandwidth limitations and distortion introduced by chromatic dispersion in the fiber. The complex filter is implemented by combining four distributed analog finite-impulse response (FIR) filters to obtain the necessary response. The filter delays are implemented using active delay cell structures to create a compact solution. The analog filter is implemented in a 55-nm BiCMOS technology and consumes 185-mW core power for five complex filter taps. Performance is evaluated using the S-parameter measurements, noise and linearity measurements, and real-time system experiments using 112-Gb/s 16-QAM-modulated signals

Frequency diversity wideband digital receiver and signal processor for solid-state dual-polarimetric weather radars

2012 Summer.Includes bibliographical references.The recent spate in the use of solid-state transmitters for weather radar systems has unexceptionably revolutionized the research in meteorology. The solid-state transmitters allow transmission of low peak powers without losing the radar range resolution by allowing the use of pulse compression waveforms. In this research, a novel frequency-diversity wideband waveform is proposed and realized to extenuate the low sensitivity of solid-state radars and mitigate the blind range problem tied with the longer pulse compression waveforms. The latest developments in the computing landscape have permitted the design of wideband digital receivers which can process this novel waveform on Field Programmable Gate Array (FPGA) chips. In terms of signal processing, wideband systems are generally characterized by the fact that the bandwidth of the signal of interest is comparable to the sampled bandwidth; that is, a band of frequencies must be selected and filtered out from a comparable spectral window in which the signal might occur. The development of such a wideband digital receiver opens a window for exciting research opportunities for improved estimation of precipitation measurements for higher frequency systems such as X, Ku and Ka bands, satellite-borne radars and other solid-state ground-based radars. This research describes various unique challenges associated with the design of a multi-channel wideband receiver. The receiver consists of twelve channels which simultaneously downconvert and filter the digitized intermediate-frequency (IF) signal for radar data processing. The product processing for the multi-channel digital receiver mandates a software and network architecture which provides for generating and archiving a single meteorological product profile culled from multi-pulse profiles at an increased data date. The multi-channel digital receiver also continuously samples the transmit pulse for calibration of radar receiver gain and transmit power. The multi-channel digital receiver has been successfully deployed as a key component in the recently developed National Aeronautical and Space Administration (NASA) Global Precipitation Measurement (GPM) Dual-Frequency Dual-Polarization Doppler Radar (D3R). The D3R is the principal ground validation instrument for the precipitation measurements of the Dual Precipitation Radar (DPR) onboard the GPM Core Observatory satellite scheduled for launch in 2014. The D3R system employs two broadly separated frequencies at Ku- and Ka-bands that together make measurements for precipitation types which need higher sensitivity such as light rain, drizzle and snow. This research describes unique design space to configure the digital receiver for D3R at several processing levels. At length, this research presents analysis and results obtained by employing the multi-carrier waveforms for D3R during the 2012 GPM Cold-Season Precipitation Experiment (GCPEx) campaign in Canada

Large scale reconfigurable analog system design enabled through floating-gate transistors

This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.Ph.D.Committee Chair: Hasler, Paul E.; Committee Member: Anderson, David V.; Committee Member: Ayazi, Farrokh; Committee Member: Degertekin, F. Levent; Committee Member: Hunt, William D

Current mode analog and digital circuit design

In this dissertation, two important current mode circuit design subjects have been explored. In the first part, the switched-current circuit technique has been investigated. The fundamental performance and limitations of this technique are explored. One of the major limitations, the signal distortion caused by clock feedthrough has been substantially reduced by a newly developed clock feedthrough cancellation technique. In addition, a filter synthesis technique has been developed by directly simulating the structure of digital filter. Several experimental CMOS prototypes have been designed and fabricated. The measured frequency and phase responses demonstrated the feasibility of this synthesis technique. In the second part, a new logic family called current-steering logic has been developed. The fundamental performance and characteristics of this technique have been discussed including the basic inverter and NOR gate with DC analysis, transient analysis and power-delay product. It has been shown that the current-steering logic has, a much smaller current spike than conventional CMOS logic circuits, which is especially desirable in mixed-mode applications. Several experimental prototypes have verified the functionality and performance of this new technique

Progress of analog-hybrid computation

Review of fast analog/hybrid computer systems, integrated operational amplifiers, electronic mode-control switches, digital attenuators, and packaging technique

Analog baseband circuits for WCDMA direct-conversion receivers

This thesis describes the design and implementation of analog baseband circuits for low-power single-chip WCDMA direct-conversion receivers. The reference radio system throughout the thesis is UTRA/FDD. The analog baseband circuit consists of two similar channels, which contain analog channel-select filters, programmable-gain amplifiers, and circuits that remove DC offsets. The direct-conversion architecture is described and the UTRA/FDD system characteristics are summarized. The UTRA/FDD specifications define the performance requirement for the whole receiver. Therefore, the specifications for the analog baseband circuit are obtained from the receiver requirements through calculations performed by hand. When the power dissipation of an UTRA/FDD direct-conversion receiver is minimized, the design parameters of an all-pole analog channel-select filter and the following Nyquist rate analog-to-digital converter must be considered simultaneously. In this thesis, it is shown that minimum power consumption is achieved with a fifth-order lowpass filter and a 15.36-MS/s Nyquist rate converter that has a 7- or 8-bit resolution. A fifth-order Chebyshev prototype with a passband ripple of 0.01 dB and a −3-dB frequency of 1.92-MHz is adopted in this thesis. The error-vector-magnitude can be significantly reduced by using a first-order 1.4-MHz allpass filter. The selected filter prototype fulfills all selectivity requirements in the analog domain. In this thesis, all the filter implementations use the opamp-RC technique to achieve insensitivity to parasitic capacitances and a high dynamic range. The adopted technique is analyzed in detail. The effect of the finite opamp unity-gain bandwidth on the filter frequency response can be compensated for by using passive methods. Compensation schemes that also track the process and temperature variations have been developed. The opamp-RC technique enables the implementation of low-voltage filters. The design and simulation results of a 1.5-V 2-MHz lowpass filter are discussed. The developed biasing scheme does not use any additional current to achieve the low-voltage operation, unlike the filter topology published previously elsewhere. Methods for removing DC offsets in UTRA/FDD direct-conversion receivers are presented. The minimum areas for cascaded AC couplings and DC-feedback loops are calculated. The distortion of the frequency response of a lowpass filter caused by a DC-feedback loop connected over the filter is calculated and a method for compensating for the distortion is developed. The time constant of an AC coupling can be increased using time-constant multipliers. This enables the implementation of AC couplings with a small silicon area. Novel time-constant multipliers suitable for systems that have a continuous reception, such as UTRA/FDD, are presented. The proposed time-constant multipliers only require one additional amplifier. In an UTRA/FDD direct-conversion receiver, the reception is continuous. In a low-power receiver, the programmable baseband gain must be changed during reception. This may produce large, slowly decaying transients that degrade the receiver performance. The thesis shows that AC-coupling networks and DC-feedback loops can be used to implement programmable-gain amplifiers, which do not produce significant transients when the gain is altered. The principles of operation, the design, and the practical implementation issues of these amplifiers are discussed. New PGA topologies suitable for continuously receiving systems have been developed. The behavior of these circuits in the presence of strong out-of-channel signals is analyzed. The interface between the downconversion mixers and the analog baseband circuit is discussed. The effect of the interface on the receiver noise figure and the trimming of mixer IIP2 are analyzed. The design and implementation of analog baseband circuits and channel-select filters for UTRA/FDD direct-conversion receivers are discussed in five application cases. The first case presents the analog baseband circuit for a chip-set receiver. A channel-select filter that has an improved dynamic range with a smaller supply current is presented next. The third and fifth application cases describe embedded analog baseband circuits for single-chip receivers. In the fifth case, the dual-mode analog baseband circuit of a quad-mode receiver designed for GSM900, DCS1800, PCS1900, and UTRA/FDD cellular systems is described. A new, highly linear low-power transconductor is presented in the fourth application case. The fourth application case also describes a channel-select filter. The filter achieves +99-dBV out-of-channel IIP2, +45-dBV out-of-channel IIP3 and 23-μVRMS input-referred noise with 2.6-mA current from a 2.7-V supply. In the fifth application case, a corresponding performance is achieved in UTRA/FDD mode. The out-of-channel IIP2 values of approximately +100 dBV achieved in this work are the best reported so far. This is also the case with the figure of merits for the analog channel-select filter and analog baseband circuit described in the fourth and fifth application cases, respectively. For equal power dissipation, bandwidth, and filter order, these circuits achieve approximately 10 dB and 15 dB higher spurious-free dynamic ranges, respectively, when compared to implementations that are published elsewhere and have the second best figure of merits.reviewe

Matrix Transform Imager Architecture for On-Chip Low-Power Image Processing

Camera-on-a-chip systems have tried to include carefully chosen signal processing units for better functionality, performance and also to broaden the applications they can be used for. Image processing sensors have been possible due advances in CMOS active pixel sensors (APS) and neuromorphic focal plane imagers. Some of the advantages of these systems are compact size, high speed and parallelism, low power dissipation, and dense system integration. One can envision using these chips for portable and inexpensive video cameras on hand-held devices like personal digital assistants (PDA) or cell-phones In neuromorphic modeling of the retina it would be very nice to have processing capabilities at the focal plane while retaining the density of typical APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our MAtrix Transform Imager Architecture (MATIA) that uses analog floating--gate devices to make it possible to have computational imagers with high pixel densities. The core imager performs computations at the pixel plane, but still has a fill-factor of 46 percent - comparable to the high fill-factors of APS imagers. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting data-flow architecture can directly perform all kinds of block matrix image transforms. Since the imager operates in the subthreshold region and thus has low power consumption, this architecture can be used as a low-power front end for any system that utilizes these computations. Various compression algorithms (e.g. JPEG), that use block matrix transforms, can be implemented using this architecture. Since MATIA can be used for gradient computations, cheap image tracking devices can be implemented using this architecture. Other applications of this architecture can range from stand-alone universal transform imager systems to systems that can compute stereoscopic depth.Ph.D.Committee Chair: Hasler, Paul; Committee Member: David Anderson; Committee Member: DeWeerth, Steve; Committee Member: Jackson, Joel; Committee Member: Smith, Mar

Ultra-low-power circuits and systems for wearable and implantable medical devices

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 219-231).Advances in circuits, sensors, and energy storage elements have opened up many new possibilities in the health industry. In the area of wearable devices, the miniaturization of electronics has spurred the rapid development of wearable vital signs, activity, and fitness monitors. Maximizing the time between battery recharge places stringent requirements on power consumption by the device. For implantable devices, the situation is exacerbated by the fact that energy storage capacity is limited by volume constraints, and frequent battery replacement via surgery is undesirable. In this case, the design of energy-efficient circuits and systems becomes even more crucial. This thesis explores the design of energy-efficient circuits and systems for two medical applications. The first half of the thesis focuses on the design and implementation of an ultra-low-power, mixed-signal front-end for a wearable ECG monitor in a 0.18pm CMOS process. A mixed-signal architecture together with analog circuit optimizations enable ultra-low-voltage operation at 0.6V which provides power savings through voltage scaling, and ensures compatibility with state-of-the-art DSPs. The fully-integrated front-end consumes just 2.9[mu]W, which is two orders of magnitude lower than commercially available parts. The second half of this thesis focuses on ultra-low-power system design and energy-efficient neural stimulation for a proof-of-concept fully-implantable cochlear implant. First, implantable acoustic sensing is demonstrated by sensing the motion of a human cadaveric middle ear with a piezoelectric sensor. Second, alternate energy-efficient electrical stimulation waveforms are investigated to reduce neural stimulation power when compared to the conventional rectangular waveform. The energy-optimal waveform is analyzed using a computational nerve fiber model, and validated with in-vivo ECAP recordings in the auditory nerve of two cats and with psychophysical tests in two human cochlear implant users. Preliminary human subject testing shows that charge and energy savings of 20-30% and 15-35% respectively are possible with alternative waveforms. A system-on-chip comprising the sensor interface, reconfigurable sound processor, and arbitrary-waveform neural stimulator is implemented in a 0.18[mu]m high-voltage CMOS process to demonstrate the feasibility of this system. The sensor interface and sound processor consume just 12[mu]W of power, representing just 2% of the overall system power which is dominated by stimulation. As a result, the energy savings from using alternative stimulation waveforms transfer directly to the system.by Marcus Yip.Ph.D