I EES SERIES REPORT NO. 12 I L i --. I ! https://ntrs.nasa.gov/search.jsp?R=19670016742 2020-03-12T11:27:51+00:00Z PROCEEDINGS F ~ E M S ~ , OF TH.. 1966 Grpnino Arthur Korn was born in Berlin, Germany, on May 7, 1922. He was gradu- - ated from Brown Uni- versity, Providence, R. I., in 1942, and re- ceived the M.A. and , Ph.D. degrees in phys- ics from Columbia University, New York, N. Y.,and Brownin 1943and 1948, respectively. After wartime service in the U. S. Navy, he was, successively, a Project Engineer with Sperry Gyroscope, Great Neck, N. Y., head of the analysis group a t Curtiss-Wright/Columbus, a staff engineer with Lockheed/Burbank, and a consultant under his own name. Since 1957, he has been a Professor of Electncal Engineering at the University of Arizona, Tucson, where he teaches courses on electronic computers and random-process measurements; he is also a Director of Computer Research, Inc., Lafayette, Calif. With his wife, Theresa M. Korn, he is the author of Electronic Analog Computers (1952 and 1956), Mathematical Handbook for Scien- tists and Engineers (1 961), Electronic Analog and Hybrid Computers (1964), Basic Tables for Electrical Engineering (1 969, Random-Process Simulation and Measurements (1966), and Man- ual of Mathemarics (1966). He is coeditor-in chief of the McGraw-Hill Computer Handbook (1962) and the Digital Cornpurer User’s Hand- book ( I 967) and has contributed articles to seven other engineering handbooks. He edits Mc- Graw-Hill’s new series of short numerical tables and is chairman of the editorial board of Simu- lation. He has taught in Mexico and surveyed engineering education in Chile as a Consultant to the National Academy of Sciences. Dr. Korn is a member of Sigma Xi, Simula- tion Councils, Inc., and the International Ana- log Computer Association. Progress of Analog /Hybrid Computation G . A. KORN A bstroct-Solid-state circuits and the integrated circuits succeeding them are improving analog-computing-element reliability by an order of magnitude, speed by two orders of magnitude, and still reducing system cost. The effects of integrated-circuit technology on the price, reliability, and sophiiticetion of digital computers are even more pronounced, and, the result- ing systemdesign t‘radeoffs shape the future course of hybrid-computer tech- niques. This review article discusses the design of fast analogihybrid com- puter systems, including recent developments in integrated operational amplifiers, electronic mode-control switches, digitdl attenuators, and new packaging techniques. SURVEY OMPUTERS are physical systems designed to imple- ment the idealized relationships of mathematical c models. Computers are conventionally classified as analog.. computers if the machine variables representing mathematical quantities are considered to vary continu- ously (voltages, shaft rotations), while a digital computer is a discrete-state system. The engineer’s most noticeable im- pression of an analog computer is likely to be a fast, only moderately accurate differential-equation solver (differen- tial analyzer) employing separate (parallel) analog comput- ing elements to implement each mathematical relation; while the most important digital computers perform nu- merical operations accurately and sequentially and incor- porate considerable decision-making ability and a large memory to permit stored-program control of computation and iterative operations. Advancing technology has evolved Manuscript received August 16, 1966. This work is one of the Uni- versity of Arizona’s ASTRAC 11 and LOCUST projects, under NASA Grant NsG-646, together with various grant supplements and institutional grants. The APE I1 educational iterative differential analyzer was de- veloped under NSF Grant GY-379; ASTRAC I1 was begun under joint NASA/U. S. Air Force sponsorship. The author is with the University of Arizona, Tucson, Ariz. the familiar analog computer into a wide class of hybrid- analog-digital computers which may combine high analog computing speed with accurate digital operations, decision making, and memory. Computers, analog, digital, or hybrid, have two principal applications. They may set up mathematica! relations to produce desired unknown or otherwise desired quantities and/or functions (problem solving, simulation of engineer- ing systems). The second (and at least as important) applica- tion of computing devices is as system components used for instrumentation, control, and display : here, the computer forces at least a portion of a reluctant physical system to act like a mathematical model and thus recreates it nearer to the heart’s desire. Up to 1960, the simulation of dynamic systems such as aircraft, missiles, space vehicles, and nuclear and chemical plants was accomplished almost entirely by means of elec- tronic analog computers. The parallel computing elements of such machines permit high-speed real-time solution of differential equations, and establish a block-diagram- oriented, live mathematical model offering a good deal of intuitive insight into system operation. “Hands on” changes of system parameters, programs, and subsystems are readily possible with analog computers; solutions can be observed on multi-trace and xy recorders to provide the investigator with immediate feedback about the results of system changes. Analog-computer studies of large dynamic sys- tems also show up significant disadvantages of this type of computation ; the relatively low component accuracies per- mit long-term trajectory studies only if sophisticated mathe- matical perturbation techniques are applicable, and such techniques destroy much of the intuitive insight of direct 2 analog computing e lements DECEMBER m- * PROCEEDINGS OF THE IEEE ' +p onoioq com,ytors I -0- switchad analog Computing elements 1 , - 1 , - c I -a I -- A A t t T T digital logic and timing c i r c u l t s , b r o u g h t o u t to control ("digi ta l") p a t c h b a y 0 cont ro l - p a t c h b a y t e r m i n a t i o n (a) Fig. 1. (a) Iterative-differential-analyzer operation. (b) Flow diagram. The principal operations are analog-computer (differential-analyzer) runs simulating a physical system, as ordered by electronic switches actuated by corresponding digital control variables U,. Control-vari- able changes may be preset by timers and counters and/or "computed" by analog comparators and digital logic. Switches and comparators form the digital-analog and analogdigital interfaces. Typical applica- simulation. Moreover, scale factor estimation and problem checkout can become very cumbersome. Improved simulation techniques combining analog and digital computation take two essential forms, which are often used in combination. An iterative diflerential analyzer is an electronic analog computer incorporating analog memory in the form oftrackLhold circuits and equipped with analog comparators, patchable digital logic elements, and comparator- or logic-operated D / A switches, and timing circuits (Fig. 1). Such machines have, thus, a measure of the memory and decision-making ability of a digital computer ; integrator mode control and, to some extent, analogcomputer pro- grams and system parameters can be changed by the digital logic which, in turn, takes account of analog- comparator decisions. This permits complex subroutine control, branching, simulation of digital computers, multi- plexing of computing elements, and, above all, automatic iteration and system optimization. The iterative differential analyzer is a t its best in its more recent ultra-high-speed versions permitting iteration of as many as 2000 complete system simulations per second under digital-logic control. Such fast iterative computations permit rapid computation of statistics (Monte Carlo methods), so that the system de- signer receives practically immediate feedback of the effects of system parameter changes on statistics, and automatic optimization of statistics becomes possible (Fig. 2) [ 2 ] . s t a t e given (START) s ta r t ing conditions operation (subroutine, computer run 1 performed by computing elements daclsion mad. by analog - comparator and digital logic 1 I I o p e r a t i o n - decision made by preset timar or subroutine counter go to next subroutine, stop, etc, (b) tions are to iterative optimization of the simulated system and to statistical computations. A small or large general-purpose digital com- puter may be added and will communicate with the analog computer via A/D and D/A converters, and with the control logic via interrupt and sense lines and by digital commands fed into the control patch- bay [19]. True combined analog-digital simulation with an analog computer (usually an iterative differential analyzer) joined to a general-purpose digital computer through a converter linkage [ 1 ] has permitted real-time simulation of large and very complicated systems. The digital computer is, in par- ticular, employed for accurate and relatively slow trajec- tory integration, while the analog computer deals with the high-speed dynamics ; in addition, the digital computer can conveniently store and/or compute complicated functions of several variables and, also, perform many housekeeping tasks such as potentiometer setup, static checking, and the computation of accurate check solutions. Combined simu- lation is often made mandatory by stringent combinations of speed and accuracy requirements. But it should be remembered that combined simulation joins not only the advantages of analog and digital computers but their dis- advantages as well, for the simulation suffers both from the low precision of the analog computer and the sampled-data bandwidth limitation of the digital machine. In addition, large combined systems tend to be complex and very ex- pensive, and the difficult and sophisticated programming required destroys much ofthe intuitive appeal of the simula- tion. By contrast, the use of one of the increasingly inexpensive small (12- to 16-bit) general-purpose data processors as an- immeasurably improved-logic and control unit for a fast iterative dlflerential analyzer has proved to be an extra- 1% 0 a hPsEuDo- 43 a SIMULATED SYSTEM RANDOM- SIGNAL GENERATOR WITH OUTPUTS * COMROL ,NOISE PRODUCTION STATISTICS OUTPUT \ MULTIPLE TOLERANCES * J KORN: ANALOGBYBRID COMPUTATION 3 I Fig. 2. This example illustrates the possibilities of combining a fast iterative analog computer with a small stored-program digital data processor. Analog computing elements produce successive samples of the squared-error time average 200 Hz, signal frequencies > 2 kHz) is to statistical applications (Monte Carlo simulation), to rapid system optimization, and to combinations of these (Fig. 2). The real advantage of fast computation is not the mass production of data (this could be done by a digital computer working at night), but the possibility of direct on-line- operator interaction with the results from, say, a sample of 1000 computer runs completed in a second or less. As a matter of competitive advertising, most commer- cially available analog/hybrid computers offer repetitive operation at 1000 computer runs per second, but this is usually wholly misleading. It is easy to supply computer- reset pulses at 1 kHz, but meaningful computation a t such iteration rates requires, at least, component accuracies within 0.2 percent at signal frequencies of 5 to 10 kHz. It is instructive to investigate just what such a requirement means. Before one can even think of dealing with possible amplitude errors, it is necessary to control errors due to phase shift and switching time delays [l] . The effects of phase shift in amplifiers and passive networks and those of time delays caused by late operation of integrator and track-hold mode-control switches and analog comparators cause quite similar delay errors, as illustrated in Fig. 3. Given a signal waveform changing at the rate 2na (typically a sinusoidal voltage a cos 27cft of frequency f Hz), a timing error of At seconds, or an equivalent phase-shift error, A# radians cause the true percentage error t; = 200~JAt = lOOA4. (1) The “magic equation” ( 1 ) spells the doom of high-frequency computation with most commercially made equipment. Con- sider the very lenient requirement of 0.2 percent error at a computing frequency of 5 kHz. This requires : 1) Phase-shift errors A+ below 0.002 radians or about 0.12 degrees at 5 kHz. Even in a unity-gain phase in- verter, this requires amplifiers with a zero-dB cross- over frequency of I O MHz with a 20 dB/octave roll- off, and perhaps 2 MHz for a less conservative rolloff. The situation becomes exactly ten times worse for a gain-of-IO phase inverter, not to speak of multipliers and function generators. Nevertheless, such require- ments can be met with * IO-V feedforward amplifiers (described further in the following) and clever equalization. 2) The above phase-shift requirements extend to all passive networks, attenuators, and interconnection lines (if any) in the computer. Distributed capacitances make the 100-K resistors used in commercial analog computers act like veritable delay lines at high fre- quencies. While some of these ills can be cured with equalizing capacitors, probably the best solution is the use of 1-K to 10-K summing resistors and similarly low impedance levels in all attenuators. Solid-state computing elements can be mounted directly behind I966 Fig. 4 KORN : ANALOG/HYBRID COMPUTATION VOLTAQE r CORRECT WAVVEFORY 1 ’ d TIYINQ ERROR At Fig. 3. Timing errors A/ or phase errors AI#J= 2nfAr are crucial in fast analog computation. . .. Operating with signal frequencies as large as 60 kHz. the digitally controlled ASTRAC I 1 here displays the complete input-output cross- correlation function of a fast-time simulated control system with the analog-computer patchbay without any inter- connecting lines. 3) A glance a t the “magic equation” ( 1 ) shows clearly that 0.2 percent accuracy at 5 kHz requires all integra- tor mode-control switches to initiate computation within 65 ns of one another. Such diferential switch- ing times for integrators and track-hold circuits are possible only if the total switching time is below about 200 ns. 4) If an analog comparator or D/A switch must respond in the course of a computer run, its total (not differen- tial) response time must be within 65 ns. Fortunately, most fast iterative computation requires comparators to respond to track-hold outputs only, so that timing does not cause errors. A frequently redeeming feature is the fact that the highest 5 random input once every second. The operator can immediately assess effects of system-parameter changes on statistics computed from hun- dreds of analog-computer runs. signal-frequency components constitute only, say, 10 per- cent of the total analog signal, so that the total percentage error is reduced. In any case, (1) indicates that some com- mercially available analog computers can compute with fair accuracy at repetition rates of the order of 50 to 200 Hz. The ASTRAC 11 and LOCUST iterative analyzers (Fig. 4) developed at the University of Arizona under NASA and U. S. Air Force sponsorship do permit 1 kHz iteration; unity-gain-inverter phase shift is below 0.1 deg at 10 kHz, with integrator differential switching times below 20 ns, and comparator response time below 80 ns. SOME HYBRID-COMPUTER SYSTEM CONSIDERATIONS Since their inception about a decade ago, combined analogdigital computer systems have developed from true monstrosities into reasonably finished hardware; software and programming know-how are still lagging component 6 PROCEEDINGS OF THE IEEE DECEMBER COMPUTER L I N K A O E Fig. 5. Simplified hybrid-computer loop. developments. In addition to the usual computing errors in- herent in analog and digital computers as such, the hybrid- computer system (Fig. 5) adds some errors of its own; these error sources are nicely discussed in [3]-[7]. Briefly, the errors due to hybrid-computer operation as such are : 1) Conversion errors dbe to poor A/D and D/A con- verters. 2) Quantization errors due to the finite number of digital bits; with the usual 13- to 14-bit systems, these are rarely serious and can often be further reduced through the application of dither [2]. Reference [6] presents a sophisticated theory for quantization-error estimation, but the best estimates are obtained by digital-computer test routines which simply reduce the number of bits used for a test run. 3) Errors due to digitalprocessing and conversion time de- lays. While elaborate studies of such errors by means of Z-transform analysis are possible at least for linear systems [4], [ 5 ] , we can simply consider the entire digital computer and linkage (Fig. 5) as an analog computing element having a time-delay error At; then the “magic equation” ( I ) estimates the component error, which in each hybrid-computer setup affects the solution very much like a phase-shift error A+ = 2nfAt for sinusoidal components of frequencyf. 4) Skewing errors due to nonsimultaneous analog-digital and/or digital-analog conversion of different computer variables. To minimize the effects of the various timing errors, one makes the processing delay At constant through suitable interruptions of the digital computation. Partial compensa- tion of the time-delay error is then obtained with the aid of ordinary lead networks ahead of the analog-to-digital con- verter, or by the more sophisticated method of predictive extrapolation, either in the digital computer or with extra- polating digital-to-analog converters [ I ], [ 5 ] , [7]. The processing delay Ar is essentially reduced to the time taken for the digital computations on each analog sample if the digital computer is equipped with a direct memory-access channel. With this option, which should be included in every digital computer used for hybrid computation, it will usually be found that the skewing errors are small compared to the time-delay errors. ANALOG-SYSTEM COMPONENTS We turn next to the design of the analog-computer system. f 100-V analog computing elements may be preferred for optimal accuracy in “slow” simulation, because static accuracy in nonlinear computing elements is less expensive to obtain and maintain in a 100-V system. Note, however, that static errors within 0.02 percent of half-scale can be maintained with If: 10-V summers and multipliers as well as with f 100-V components [7]. IO-V amplifiers can be faster and less costly than f 100-V amplifiers; but the main advantage of f 10-V systems is the possibility of utilizing lower computing impedances to improve bandwidth, integrator drift, and computer noise. Miniaturization, which brings further bandwidth advantages, is also man- aged more easily at +_ 10-V because of the reduced heat- dissipation requirements. The most accurate “slow” analog computers still employ wirewound resistors, but these are giving way to new preci- sion metal-film resistors, at least wherever bandwidth is a consideration. Carbon-film resistors may be regarded as obsolete for analog-computer applications. In the most accurate analog computers, capacitor dielec- tric absorption, calibration, electroelastic. thermal, and hysteresis effects are critical accuracy-limiting factors; they cause component errors of the order of 0.02 percent [ I ] . Fine-grain polystyrene film is still the preferred dielectric. Compression trimming of plastic-film capacitors. which implies the possibility of mechanical deformation of foil and dielectric, is apt to cause more trouble than i t cures. A significant step forward was the 1965 development of a simple equalizer circuit [8] capable of reducing dielectric- absorption effects to below 0.005 percent. An important consequence is the possibility of a more favorable com- promise between capacitor dielectric absorption and the temperature coefficient of capacitance. The hybrid-computer era has seen relatively little im- provement in the design of analog multipliers and function generators, although it is now possible to compensate both special-purpose and general-purpose diode function genera- tors accurately for diode-breakpoint drift with temperature by including matched diodes in the bias supplies [7]. Diode quarter-square multipliers have almost entirely displaced servos and time-division multipliers and have attained com- ponent accuracies of better than 0.05 percent of half-scale ; special wide-band multipliers havc errors as low as 0.5 per- cent at I O to 50 kHz [2]. Accurate diode quarter-square multipliers are expensive and have obvious disadvantages due to their inherent piecewise-linear approximation of the product. Some renewed investigation of time-division multi- pliers employing new types of solid-state switches may well be in order. Where bandwidth considerations permit, nonlinear op- I966 KORN: ANALOG/HYBRID COMPUTATION 7 I (b) Both show offset voltage and current sources. Fig. 6. (a) Summing amplifier. (b) Electronic integrator. TABLE I TYPICAL DRIFT ERRORS IN GENERAL-PURPOSE ANALOG COMPUTERS (1966) (Maintuined ar 25 f5 deg C, with regulated power supplies (2)) Integrated Circuit + I O V, no chopper R = 10 K f 10 V FET -input, no chopper R= 10 K to 100 K High-quality chopper-stabilized amplifier (FET chopper) +1ov f l 0 0 V R = l O K to IOOK R= 100 K to 1 M Ed - +30 pV id f30 nA I esum ( a , + a , + a , = l ) + 360 p v erum (a , +a,+u,=21) 7960 p v ein, (typical computer run, t/RC = 50) ein, (long integration, t/RC= IOOO) f 16.7 mV k0.33 V +a PV negligible f 120 p v f l . 3 mV + 3 mV k60 mV f10 p v f40 pV negligible negligible +20 pv f80 pV f 220 p v f 880 pV f 500 pV - + 2 mV - + 10 mV - +40 mV erations are performed digitally, or by multiplying D/A converters. Even after 20 years of development, setup pro- cedures for diode function generators are still cumbersome; a number of manufacturers have developed card- and patch- board-programmed diode function generators to simplify function storage. The problem of generating functions of two or more variables is as bad as ever [I ] . With small general-purpose digital computers available at prices as low as $10000, the best solution for function generation, at least in “slow” analog simulation, appears to be to utilize such a small digital computer for the generation of between five and ten analog functions: at a price of $10 000 for the digital computer, plus $5000 for a simple linkage, the cost per function is still comparable to that of commercially available card-programmed function generators [9]. LOW-DRIFT DC AMPLIFERS Solid-state dc amplifiers can have substantially lower drift than vacuum-tube amplifiers. Dc amplifier drift is specified in terms of the equivalent voltage and current offset after a given time interval, power-supply-voltage change, or tem- perature change. Referring to Fig. 6, the equivalent-input- offset voltage Ed and current i d are, respectively, defined as minus the input voltage and current needed to return the open-loop output to zero (balance condition) with a grounded voltage source and a current source at the sum- ming point. In the summer and integrator circuits of Fig. 6, the output-voltage errors due to drift, assuming high am- plifier gain, are [l ] esum = - (a, + a, + a3 + l)Ed - Rid (summer) (integrator) (2) where t is the computing time. Table I illustrates drift-error effects for typical computer dc amplifiers operated over normal room-temperature ranges. The design of high-quality solid-state dc amplifiers, both discretecomponent and integratedcircuit types, has reached a high state of development. Figure 7(b) illustrates an amplifier circuit typical of recent integratedcircuit design. It is worthwhile to list the circuit features used to obtain low drift in such amplifiers. A diflerentiul input stage with a current-source transistor in the emitter return ties the temperature dependence of the first-stage output to the diflerence of two transistor V,,’S; transistor matching for VBE and B can reduce voltage drift from 2.5 mV/deg C to as little as 5 pV/deg C [l]. Matching is especially favorable in monolithic integrated circuits; differential heating of the two input transistors must be minimized by low values of the collector current (<200 PA). The first-stage gain should be sufficiently high (at least 10) to make drift effects in later stages negligible. A roughly matched second differential-amplifier stage may 8 PROCEEDINGS OF THE IEEE DECEMBER P NOUlML ae *C ( b) Fig. 7. (a) Temperature dependence of tranhistur paramctrrs. ( h ) Typical integrated-circuit dc amplifier (himilar to Westinghouse Type I74Q). follow the first for more perfect common-mode rejection, or common-mode feedback from a succeeding stage may be used [ I 1. Differential-amplifier voltage drift can, we note in pass- ing, be reduced below 0.5 pV/deg C if the VBt temperature coefficients are matched through individual collector- current adjustments [ l ] , but this has not been applied in production. Current drift, which may be thought of as a change in input-transistor bias-current requirements, is due to changes in i,/P and in the leakage current IC,,. The latter is negligible for silicon transistors at room temperatures; at higher temperatures, the IC,, change will, in fact, counteruct the i,/B change with temperature. I t is possible to compensate for the current drift with the aid of temperature-dependent current sources comprising thermistors, diodes, or transis- tors, or to counteract changes in f l by corresponding temperature-dependent changes in i, [ I ] ; but such com- pensation schemes work best over limited temperature ranges (perhaps I O to 20°C) because of the nonlinear tem- perature dependence of /? [Fig. 7(a)]. In general, the best methodjijr reducing current drift is to usi' high$ trunsistors and to kc.ep the ,first-.stage collector currents he lo^^ 100 to 200 PA. This reduces iJP in toto and, hence, also its changes with temperature. In Fig. 7(b), the input current has been further reduced through the inclusion of commoncollector input transistors, which roughly divide the bias-current re- quirement by another factor of,!?. I t is thus possible to reduce the total input current well below 100 nA between - 50 deg C and 180 deg C . The differential-amplifier connection as such can reduce current drift only if both input transistors are connected to similar source impedances; this is rarely the case in general-purpose computers. In dc amplifiers requiring very low input currents and high input impedances, junction F E T s may replace the input transi.stol-s to reduce input currents to the order of picoampcres; MOSFET's are not recommended for dc- amplifier input stages, since they may tend to change their properties with time. The voltage drift of FET dc-amplifier stages can be reduced through selection of an optimal operating point [I21 and by matching of differential- amplifier stages. The best FET amplifiers now have about the same voltage drift as high-quality bipolar transistor stages (3 to I O pV/deg C ; also see Table I ) . I M F W ) V L D ELECTRONIC HOPPERS In accurate gencral-purpose analog computers, the possi- bility of open-loop integration of offset voltages and cur- rents still makes dc amplifier chopper stabilization [ I ] mandatory. MOSFET choppers operated at frequencies of 100 t o 1000 Hz have long-term input voltage offsets below 20 pV and negligible current offset over a wide range of temperatures. Sinusoidal drive to the input chopper reduces switching spikes. FET choppers permit low-voltage drive at higher frequencies than neon-bulb/photoresistor chop- pers and arc also more reliable. 1N.I I.GHA'I L:l~-~lHCLlI 1 C0KSII)ERAT~IONS Special integrated-circuit considerations in amplifier design require that voltage level:, depend on resistance rurios rather than resistance wluc . . s . Large resistance values should be avoidcd whenever possible, extra transistors can be added just about as easily as resistors, and transistor matching and thermal coupling must be generally excellent. While earlier types of monolithic integrated circuits had only NPN transistors. complementary transistors are readily included in more recent designs, a very important advantage. Breakdown voltages have been greatly im- proved recently. so that 10-V operation is possible with- out much adverse effect on bandwidth. New ceramic insula- tion [23] can be expected to improve monolithic dc am- plifiers still further. THE STRIKING ADVANTAGES OF FEEDFORWARD AMPLIFIERS Ferdfi,r~(,trrdurnpll~firr.s (Fig. 8) pass high-frequency-signal components through a high-pass filter directly to a wide- band output stage, while cascading a high-gain dc amplifier with the output stage for lower frequencies; the well-known chopper stabilizers for dc amplifiers arc special cases of feedforward circuits [ 1 1. The now widely used 10-V high-Ruin c h r s s A B com- plemmtury output stage of Fig. 8 can have a gain as high as 2000 at 20 kc with unity gain at 25 to 100 MHz, depending on transistors and load. I t has relatively low quiescent cur- rent and is especially well suited to feedforward operation, 1966 KORN: ANALOG/HYBRID COMPUTATION OUT - 15V 9 Fig. 8. Feedforward dc amplifier employing a fast class A B output stage and an integrated-circuit dc amplifier (LOCUST computer, University of Arizona). since high- and low-frequency signals are added without the usual mixing loss [l 1. The combination of such a feed- forward output stage with a modern low-cost integrated- circuit input amplifier yields a number of remarkable advantages : The amplifier high-frequency response i s twentiullj~ thut of a single wide-band stage followed bj- un emitter fol- lower, and no shunt rolloff networks are required for stabilization. As a result, such amplifiers can produce full f 10 V, 30 mA output all the way up to 2 MHz. The feedforward combination completel-v uvoids the usual compromise between high-frequencj. response und low-driftt/lo,c*-noise design of the dc-utnplifier input stage. If this fact were more generally realized, the current drift and low-frequency-flicker noise of many general-purpose integrated-circuit dc amplifiers could be improved by at least a factor of three by the simple expedient of reducing their input-stage collector cur- rent; the feedforward connection would take care of the frequency response. The circuit of Fig. 8, intended for the University of Ari- zona’s LOCUST iterative differential analyzer, combines a commercially available, low-cost, low-drift integrated- circuit amplifier with the discrete-circuit output stage to produce a high-quality, wide-band amplifier at very low cost. A chopper-stabilizer stage can be added to permit more accurate low-frequency integration. A very similar circuit also permits the design of inexpen- sive & 100-V, 25-mA dc amplifiers: one merely replaces the class-AB complementary output stage shown in Fig. 8 by an NPN/NPN 100-V totem-pole output stage having a gain of approximately 12. IMPROVEMENTS IN ELECTRONIC MODE-CONTROL SWITCHING The computing errors caused by electronic mode-control switching for integrators and track-hold circuits are dis- cussed in detail in [ 1 1, [7], [ 161, and [ 171. In addition to the high switching speeds already discussed, high-quality elec- tronic switches must have high back resistance, low for- ward resistance, minimum voltage and current offset, and low spike-causing capacitance between logic (control) and signal circuits. Figures 9 and 10 illustrate two modern electronic switching schemes for integrator control ; others are described in [I]. In particular, the circuit of Fig. 9 employs 200 to 800 ns FET switches inside feedback loops to avoid FET forward-resistance effects; it practically duplicates the static accuracy of relay switching. The circuit also permits fast integrator resetting: in RESET, the in- tegrating capacitor charges through a low-impedance path. On the other hand. the requirement for a separate holding capacitor (in reality, one capacitor for each time scale provided), as well as multiple switching, makes this circuit quite cumbersome. Thi finite forward resistance rF of the bipolar transistor grounding the holding capacitor causes the stored value to be in error by 200 nfrFC percent for sinusoids of frequencyf‘ [ l 1. r F , which is of the order of I O ohms, will also cause some feedthrough from the integra- tor inputs in RESET. This mode-control circuit is, therefore, best suited for relatively slow, high-impedance computers. The switched-amplifier method [Fig. 10(a), (b)] used in the University of Arizona’s ASTRAC 11, APE 11, and LOCUST computers employs a switched feedback am- plifier whose very low output impedance (less than 0.2 ohms in ASTRAC 11) practically shortcircuits the effect of the integrator inputs so that they need not be opened by a separate switch in RESET. No HOLD mode is provided; all holding is done with separate track-hold circuits, which greatly simplifies digital control and improves frequency response, but may require additional equipment. Since the high-current switch is never saturated, switches of this type are the fastest integrator mode-control switches available (total switching time 40 to 80 ns, differential switching time less than 20 ns). The ASTRAC-I1 circuit is described in 10 PROCEEDINGS OF THE IEEE DECEMBER T C,", ! I c o Y c u l c H O L D R E I E T (b) Fig. 9. FET modecontrol circuit with optional HOLD circuit indicated (a) in dash lines and (b) equivalent circuits. detail in [17]; Fig. 1O(c) shows a developmental switch with a low-drift FET input stage. DIGITAL ATTENUATORS FOR COEFFICIENT SETTING Digital attenuators for coefficient setting are simplified D/A multipliers designed to switch only in the computer RESET (or POTSET) and HOLD modes. Digital attenua- tors are set up either by keyboard or, more frequently, by digital computer commands. They offer higher setting speeds and, hopefully, greater reliability than servo-set coefficient-potentiometer systems. The earliest commercially available system set the last few bits of its digital attenuators through a feedback loop similar to a servo-set-potentiometer system. This permitted the use of low-offset FET switches without special com- pensation for the FET resistances. It seems simpler, how- ever, to employ open-loop setting of bistable reed relays, which give each attenuator a nondestructive memory and use no control current during computation. After each at- tenuator is set, its output for a constant reference input is readily read out into a digital voltmeter or the digital com- puter, so that visual and/or automatic checking is still achieved. With the computer reference voltage turned off while attenuators are being set, relay contacts never in- terrupt current; they are operated well below their ratings and should last a long time. For any reasonable number of attenuators, relay switching is nor more time consuming than electronic switching: in the University of Arizona's I 1966 ----VI+- C- c- 'Y KORN: ANALOG/HYBRID COMPUTATION 11 1 T I O I O I O I I I I 2 LOOIC-CONTROLLED RELAYS F A S T INTEGRATOR INPUTS n I I I I I I +!A Fig. IO. (a) LOCUST summer/integrator employing switched-amplifier modecontrol to obtain differential switching times below 20 ns (see also [17]). Separate low- and high-impedance summing networks are used for fast and slow computation, so that three logic-switched capacitors yield five different time-scale ranges with integrator input gains all the way from IO5 s - l t o 1 s - ' . The fourth state of the two-relay combina- tion produces a low-impedance summer without any need for bottle plugs. The circuit employs a 30 MHz, k IO-V amplifier similar to that of Fig. 8. (b) Simplified equivalent circuit o fa switched-amplifier mode- control system in RESET or TRACK. (c) Switched FET-input ampli- fier proposed for the LOCUST system. PROCEEDINGS OF THE IEEE 12 DECEMBER new digital-attenuator system, C. Pracht introduced the notion of making all relay driver bistable devices (transistor flip-flops) [18], so that the digital control system can go on to set the entire attenuator system while the first few relays are still settling. All attenuators are thus set in little more than the time required to set a single relay. The system is, in fact, so fast that it becomes possible to combine the relay- driving flip-flops into shift registers with serial input: this greatly simplifies the digital addressing of individual at- tenuators (one control line per attenuator, instead of 14 to 16). Another question to be resolved is whether digital attenua- tors should employ binary or BCD weighting. The latter favors the use of manual keyboards, while binary weighting offers equipment savings and is more natural for most digital computers. The University of Arizona's system employs binary weighting and has replaced the coefficient-setting keyboard by a digit switch presetting a BCD counter; the latter counts the preset number ofclock pulses into a binary counter/shift register, which can also accept parallel input from the digital-computer output bus and controls at- tenuator settings [18]. All manual settings are read back a t once on the computer digital voltmeter. The reader may have begun to note that the design of a practical digital-attenuator system is a rather sophisticated problem. Figure 1 1 illustrates some attenuator-network designs; many combinations are possible. Figure 1 I(a) shows a simple binary-weighted summing network employ- ing SPDT (form C) relays to prevent capacitive feedthrough. Since the required 214 to 1 resistance range is too large, Fig. 1 I(b) implements at least the low-current branches with network transfer impedances; this circuit also permits the use of the somewhat cheaper SPST (form A or B) relays. Both Fig. I l(a) and 1 l(b) require summing-junction patching. The circuit of Fig. 1 I(c) permits patching to summing amplifier or integrator gain-of-10 or gain-of-I in- puts jf the latter are loaded as shown. The simple ladder network of Fig. 1 I(d) can be similarly patched and permits especially simple construction since an entire set of similar metal-film resistors can be deposited in a single operation. The choice of resistance values in Fig. 1 I(a) to (d) must satisfy the following requirements. 1) The load on the driving amplifier must not be larger than that of a comparable coefficient potentiometer. 2) The summing-junction-to-ground impedance of the attenuator has a lower limit determined by bandwidth specifications (Le., the attenuator must not kill the operational amplifier feedback). 3) The attenuator must not attenuate high frequencies unduly; with suitable lead capacitors, digital attenua- tors, which can be located directly behind the com- puter patchbay, should create less phase shift than co- efficient potentiometers. Note that even with the best possible resistance values, the attenuator circuits of Fig. 1 l(c) and (d) cannot produce a ir.rcn1 1 I 1/10 I O :' I Fig. I I . Digital-attenuator desigri. full gain of 1 or I O when patched into the corresponding amplifier inputs. Maximum coefficients of the order of 0.5 and 5, respectively, seem practical. To improve the network compromises. some digital- attenuator systems associate an amplifier With each digital attenuator. if the added cost of such an amplifier is ac- cepted, it would seem desirable to provide it with summing inputs and to switch the feedback network rather than the input network, so that amplifier offset and noise are not amplified together with the signal [Fig. 1 l(e)]. KORN : ANALOG/HYBRID COMPUTATION 13 1966 Fig. 12. These ASTRAC [ I + IO-V computingelements plugdirectly into the rear of the shielded analog-computer patchbay (Univcrsity of Arizona). NEW PACKAGING TECHNIQUES To improve maintainability and convenient system ex- pansion as well as computing bandwidth, analog computing elements ought to be plugged directly into the rear of a shielded analog-computer patchbay whenever i t is at all possible. With reasonably designed transistor and in- tegrated-circuit packages, such patchbay mounting of all analog computing elements is possible for ? 100-V as well as for k 10-V computers, although the & 100-V machine will require careful management of forced-air cooling. In the k IO-V ASTRAC 11 computer shown in Fig. 4. the on/? analog computing elements not located directly in the patchbay are the coefficient-setting potentiometers, which must necessarily be situated on the front panel. Digital at- tenuators, however, can be plugged into the patchbay, so that the last remaining analog signal wiring is eliminated. If the top and/or bottom rows of patchbay terminations are used for attenuator connections, the attenuator assemblies can be located above or below the analog patchbay, so that they do not take up much of the valuable space behind the analog patchbay. In the ASTRAC I1 and LOCUST computers, amplifiers, electronic switches, multipliers, etc., are mounted in in- dividual shielded boxes plugged into the rear of the patch- bay (Fig. 12). Figure 13 illustrates the construction ofa small educational iterative differential analyzer at much lower cost. Here, simple printed-circuit cards having a shielded ground plane on one side replace the shielded amplifier boxes. Sets of such cards bearing integrated-circuit analog and digital computing elements are plugged directly into the rear of the analog and digital patchbays. Note that the amplifier overload lights and balance controls are mounted on the front of the amplifier cards, so as to be accessible from the front panel. There is no wiring to the cards at all; even power supply wiring is supplied by spare patchbay termina- tions. Fig. 13. APE I1 amplifier card plugged into the patchbay (here removed from the computer), and an integrated-circuit logic card. I n any fast hybrid-computer system, grounding and shielding systems designed to minimize crosstalk and digital-noise effects become a first-class design problem, which must be considered from the start. Reference [22] summarizes the principal design considerations. DIGITAL CONTROL AND STATISTICAL MEASUREMENTS Integrated-circuit logic permits accurate timing and flexible control of iterative-analog-computer subroutines at very low cost. The ASTRAC II/LOCUST digital control system illustrated in Fig. 14 counts digital-clock pulses to produce not only analog-computer reset pulses but, also, precisely timed sampling pulse trains used to read out solu- tion values and to compile random-process statistics. A crystal-controlled clock provides pulses at switch-selected rates of 1000, 500. 250, 100, 50, 25, and I O kHz. A three- decade decimal counter (C,) then produces a computer- reset pulse ( R pulse) after 1000 clock pulses, so that com- puter runs or data samples can be generated at rates of 1000, 500,250, 100, 50, 25, and 10 Hz; an external clock can also be used. Counters C , and C2 are preset to produce readout sampling pulses S , , S, , , S,, S, , at digit-switch-selected multiples of 1/1000 computer run to permit flexible control of integrators, track-hold circuits, and track-hold pairs [ 1 1, [2], [ 191. The logic-switched integrator capacitors are normally slaved to the repetition-rate switch, so that time- scale changes are automatic. C , is a subroutine counter counting computer runs, comparator responses, or other events. Additional simple logic circuits produce automatic pro- gressive delay of the sampling pulses SI, SI, after a preset number of n computer runs. This “scan mode” permits sampling readout of repetitive computer solutions into slow recorders and digital computers and is also used for 14 PROCEEDINGS OF THE IEEE n CRCICT rlt- COUNTCR CONCUTCR nuns ( R I , DONCARATOR, OR R 1 n N R s2 (c) Fig. 14. (a) ASTRAC II/LOCUSTdigital-contr(~l system. (h). (c)Timing scheme. The reset period (R= I ) lasts for 100 clock pulses once every IO00 clock pulses for repetitive operation: nianually controlled real- time operation is also possible. Sampling pulses SI. S,. Sil,. S , , occur at digit-switch-selected times after the start of each computer run. Sampling pulses can also be made to advance after a programmed numhcr 01' ) t = I to 100 000 computer run5 (shown in Fig. 14(c) for ) I = I ). This permits automatic plotting o f repctitibe analog-computer wlulions and correlation functions (see also [ I 1. 121. and [19]). All thcw clock functions can be implemented with only two integrated- circuit card5 hearing multiple preset counters. Fig. 15. Analog computer. space-vehicle mockup. and digital computer are the essential components of a complex launch-system simulation. this composite photograph shows only a small portion of the comput- ing equipment committed to i~ large smiilation (Roeing Huntsville Simulation Center). 15 PROCEEDINGS OF THE IEEE, VOL. 54, NO. 12, DECEMBER, 1966 automatic DlOtting of correlation functions. Such Statistical 1121 J. R. Miller et al., Communicutions Hundbook, pt. I, Texas Instru- I measurements, an especially fruitful application of hybrid computers, are discussed in detail in [2] and [21]. REFERENCES [I] G. A. Korn and T. M. Korn. Electronic Analog and Hybrid Com- puters. New York: McGraw-Hill, 1964. [2] G. A. Korn, Random-process Simula/ion and Measurements. New York: McGraw-Hill, 1966. [3] J. McLeod, Simulation: Dynamic Modelling ofrhings and Ideas. New York: McGraw-Hill, to be published, 1967. [4] W. J. Karplus, “Error analysis of hybridcomputer systems,” Simula- tion, vol. 6, pp. 120-136. February 1966. [5] E. G. Gilbert, “Dynamic-error analysis of digital and combined analog-digital computer systems,” Simubtion, vol. 6, pp. 241-257, April 1966. [6] J. Vidal and W. J. Karplus, “Characterization and compensation of quantization errors in hybrid-computer systems,” IY65 IEEE In- temat‘l Cony. Rec., pt. 3. pp. 2 3 6 241. [7] W. Giloi, A. Kley, and G. Meyer-Brotz. “Arbeiten iiber Analog- Rechentechnik, Telefunken Z/p.. vol. 39, no. I , 1966. [8] C. H. Single, U . S. Patent Applicirtion. 1965. [9] D. M. Tutelman. ”A hybrid-computer technique for nonlinear- function generation,” Simulation, vol. 6. pp. 308-322, May 1966. [ I O ] G. Meyer-Brotz and A. Kley. “The design of d-c amplifiers with high common-mode rejection,” Electron. Engrg.. February 1966. [ I 1 ] -, Zur Verbesserung der Bandbreite gegengekoppelter Verstarker durch Vonvartskoppelung. Arch. Elek. Uhertrugung., vol. 19. p. 546. 1965. Measurement of Phase Shift In analog computer circuitry, the iieetl for nwurate phase iiieasiireiilents often arises. Inverting aiupliliers c o n t r i h t c siK- nificant phase shifts a t frequciicics well below the 3-db frequency. These phase shifts cause large errors i n R prol)leiii solu- tion. Conventional phase measuring equip- ment does not operate a t the higher fre- queiicies where high-speed compiitcrs iiow operate. A simple procedure has k e n developed which utilizes a dual t)eam oscilloscope, or a n y indicating d e \ k c with a differential input, to measure the phase shift between two sinusoids. Consider the differenre of t\vo sinusoid?; whose phase shift is to be deteriiiined. h’( l j = a sin io1 - b sin (E,/ + 6 ) . ( 1 ) B y siiiiple trigonometric inanipulatioii, E(t ) niay be expressed a s follows: E(1) = [a2 f b2 - 2 a b c o ~ 6 ] ~ ~ ~ [ s i n (a*/ 4- a)] (2) where Assume that the amplitude ~f the secoiitl sinusoid is adjusted until the amplitude - - ments, Inc., Dallas, Tex., 1965. [I31 T. B. Bergersen. “Field effect transistors in chopper and analog switching circuits,” Motorola Semiconductor Products, Inc., Phoe- nix, Ariz., Application Note 220, 1965. 1141 R. J. Widlar, “A monolithic operational amplifier,” Fairchild Semi- conductor, Mountain View, Calif., Appl. Bull. 105/2,1965. [I51 S. T. Robertson and J. J. Wisseman, “High-performance integrated operational amplifiers,” MOtOrOkd Semiconductor Products, Inc., Phoenix, Ariz., Application Note 204, 1965. [I61 G. A. Korn, “Performance of operational amplifiers with electronic mode switching,” IEEE Trans. on Electronic Computers, vol. EC-12, pp. 310-312, June 1963. [I71 H. R. Eckes, “A fast mode-control switch for iterative differential analyzers,’’ IEEE Truns. on Electronic Computers, vol. EC-14, pp. 946950, December 1965. [I81 C. Pracht, M.S. thesis. Dept. of Elec. Engrg., University of Arizona, 1966, in preparation. [I91 H. R. Eckes, and G. A. Korn, “Digital program control for iterative differential analyzers,” Simulation, vol. 2, pp. 33-41, February 1964; see also [ I 1. (201 G. A. Korn, “Hybridcomputer techniques for measuring statistics from quantized data,” Simulution, vol. 4, pp. 229-239, April 1965; see also [2]. [21] -, “Hybridcomputer Monte-Carlo techniques,” Simulation, vol. 5 , pp. 234245, October 1965; see also [2]. [22] -, “Reduction of digital noise in hybrid analogdigital com- puters.” Simulation, vol. 6, pp. 151-1 52, March 1966. [23] M. Leeds, “Better isolation boosts IC performance,” Electronic De- sign, vol. 14, pp. 17-19, September 1966. of the difference signal is a niinimuni. This conditioii occurs when b = a cos 0, (3 ) as siinple diflereiitiation of the amplitude of E ( t ) will show. I‘nder this minimuin rondi- t i o n the differelice sigiial is given by I*.’(/) = u sin e sin (id + a). (4) ‘1‘0 dcterniine the unknown phase differ- ence 6 between a sin uit and b sin (wt +e), (e.g., amplifier input and output!), apply these voltages to the diflerential input of a l’eklronix or siniilar osrilloscope, and vary the serond input gain so as lo minimize the difcrence signal seen on the screen. The ratio of the difference amplitude to u equals sin e, the sine of the desired phase angle. I t is still necessary to determine the quadrant in which e is to be found. Unless this is known u priori, it becomes necessary to either view the waveforms on a dual- trace scope or examine the zero crossings in a logiral fashion to determine the qudarant. 111 addition, the sensitivity of the null is quite poor for angles close to multiples of 90”. For such angles, it would be necessary to compare the signal whose phase angle is t o be determined with COS wt, rather than sin ut. HOWARD HANDLER Dept. of Elec. Engrg. University of Arizona Tuscon, Ariz. Aco ust ical si m u lat i o n corn m u n icati o n c han ne1 by A. M . MANDERS, University of Florida and J . V. WAIT, University of Arizona JOHN V. WAIT received his BSEE from the University of Iowa in 1955, MSEE from the University of New Mexico in 1959, and PhD from the University of Arizona in 1963. He has worked in the general field of computing and signal processing systems for a number of years, and has published papers on hybrid-code differential analyzers, binary correlators, and hybrid computer circuit design. More recently he has held teaching positions at the University of California, Santa Barbara, and the University of Florida CENESYS facility at Cape Kennedy. In September, 1966 he returned to the high, dry lands of the Southwest, where he will again be associated with Cranino Korn’s Analog/Hybrid Computer Laboratory a t the University of. Arizona. ARNFINN MOE MANDERS was born in Oslo, Norway in 1932. He came to the United States in 1955 after completing his studies a t Schous Institute of Technology in Oslo. In 1957 he received the BS and MS degrees in Electrical Engineering from Michigan Technological University and in 1963 the PhD in Electrical Engi- neering from the Polytechnic Institute of Brooklyn. Dr. Manders has been employed by Western Electric, IBM Research, and ITT. He has served as instructor a t PBI and Assist- ant Professor a t MIT. Since 1964 he has been employed by the University of Florida, CENESYS, where he is a n Associate Pro- fessor of Electrical Engineering. He is currently conducting re- search in coding and design of signals for fading channels. SUMMARY Experimental studies of fading RF communication chan- nels are usually very difficult to perform under actual operating conditions. This paper describes a fading chan- nel simulator which is easily constructed and flexible in operation. Using this simulator, modulation and coding techniques suitable for use in communication and ranging equipment r a n be tested and optimized for operation dur- ing periods of severe fading. The simulator uses ultrasonic acoustical waves transmitted through water to achieve favorable changes in the space and time scales; typical fading rates are from 2 to 30 fades per second. The paper also describes simple hybrid statistical mea- surement equipment used in studying the probability dis- tributions and correlation functions of the received signals. 16 of a randomly fading INTRODUCTION Although today we normally think of simulation of systems primarily by means of analog, digital, or hybrid computing setups, we should not forget that some important phe- nomena are not easily modeled by a finite number of ordinary differential-difference equations which can then be “solved” by conventional computer methods. An important case where a different approach is re- quired is the simulation of a (randomly) fading radio-com- munication channel. Here we have a system with randomly varying, space- and time-dependent distributed param- eters. Simulation of such channels is important to the study of many communication and ranging systems. Although the establishment of a real-world channel using a conventional radio transmitter/receiver link i s not too difficult, this approach has several obvious disad- vantages : 1. Useful studies of many long-distance propagation phenomena require great distances between trans- mitter and receiver, with the attendant difficulties of logistics, off-line communication, etc. 2. Even i f the physical distance were not enough of a problem, one has the additional problem of accu- rately establishing precise, coherent frequency and time references at both ends of a long-distance channel. 3. Most real-world propagation paths do not possess a sufficient degree of stationarity in their statistical properties to permit precise, reproducible studies. 4. One cannot easily change the location of the trans- mitting and receiving stations, antennas, etc., and then return to some previous configuration for com- parative purposes. 5. The rates-of-change of real-world fading phenpmena are relatively slow, thus making statistical measure- ments tedious and time-consuming. This paper describes a relatively inexpensive channel simulator that operates with much more convenient dis- tance and time scales. It i s useful both as an instructional device and as a reliable research tool. A simple statistical analyzer for making amplitude distribution and correla- tion measurements i s also described. The technique involves the use of ultrasonic (200 kHz) acoustic waves, in .our case transmitted through a water tank. This method, although not new, is perhaps not as well known as it should be (see, e.g., reference 1). We have found the simulator to be a surprisingly stable, re- liable mechanism for studying fading-channel phenomena. For example, the envelope and phase statistics of trans- mitted signals may be studied using a variety of propaga- tion modes, including pure random (incoherent) scatter- ing, pure specular, and mixtures of random and specular. We have used the simulator in the testing of new designs for phase-lock loops and other received-signal processing systems. 17 C E N E RAL D ESCR 1 PTI 0 N Figure 1 shows a sketch of typical tank setup, including a block diagram of the associated electronics. The simu- lator consists of a 5 x 3 x 2-foot plywood tank partially filled with tap water (figure 2). Two narrow-beam ultra- sonic transducers (figure 3) are used as receiving and transmitting "antennas." Sound-absorbent material i s placed along the walls of the tanks as needed, to prevent undesired reflections and standing waves. The nominal carrier frequency is 200 kHz, correspond- ing to an acoustic wavelength of about 7mm. This short wave length allows farfield operation in a relatively small tank, and permits strong reflections from small objects. Two interesting conditions that have been studied ex- tensively are the case where all the received signal is due to reflection from random scatterers, and the case where a steady (specular) component i s added to the randomly- scattered signal. The random scattering is produced by reflecting the signal off a column of air bubbles; the spec- ular component i s produced by placing a solid reflecting object near the bubble column. The water tank (figure 2) This unit was constructed from 3/4-inch top-grade marine plywood; the corners and bottom are reinforced with 2-inch angle iron. The seams are caulked with Dow SIL- ASTlC clear sealer, and the inside walls are coated with an epoxy-based marine paint. An occasional addition of swimming-pool chlorinating compound keeps the water free of algae, etc., so that water changes are infrequent. A garden-hose siphon to a floor drain provides an ade- quate method for water removal. Acoustic transducers (figure 3) Identical units are used for transmitting and receiving. They are ordinary acoustic transducers used in marine depth finders (APELCO Model 1443A00), mounted on movable stands. They exhibit an impedance of 200 ohms and a lateral 3-dB beamwidth of k 6 . 5 degrees. Turbulence genera tors, reflectors, absorbers Rapidly varying (10-30 cps) random scattering can be obtained by bouncing the acoustic waves off a column of air bubbles that i s generated by a group of three or four ordinary aquarium aerators. Several aerators may be SUP- plied from a single small reciprocating air pump (the entire bubble system, with control valves and plastic tubing, was purchased at a local dime store). Aluminum plates and strips on movable stands serve as specular reflectors. Two- inch-thick batts of rubberized horse hair serve as effective (and surprisingly durable) signal absorbing pads. A more slowly changing turbulence may be created by using an electric heating element or motor-driven vanes. (The suggestion of using a small school of piranha-fish was discarded, due to the obvious hazards to operating per- sonnel.) :. 200 kHz - AMPLIFIER 4 4 I I I I t PRODUCT 200 kHz OSCILLATOR -,..--I. - I DEMODULATOR I I DE - I GENERATOR $ t t ENVELOPE SUBCARRIER PHASE Figure 1 -Typical tank setup, including SSB transmitter and receiver Figure 2 - Photograph of water tank Figure 3 - Photograph of acoustic transducer 18 CHANNEL CHARACTERISTICS: TYPICAL SETUPS The transmitting transducer must be driven by a signal of the order of 3-4 V peak-to-peak; a suitable driving circuit is shown in figure 4. Channel measurements indicate that the attenuation (expressed in terms of the ratio between the transmitting and receiving transducer voltage levels) may be estimated by the following formula Attenuation in dB = (IO + 0.350), where D is in inches Path lengths of over 40 inches have been successfully used. Figure 5a shows a typical setup to obtain an almost completely random scatter mode of transmission, with little or no specular component. A sample of the received signal i s shown in figure 6; it typically exhibits 5-10 deep fades per second and 20-30 minor fades per second. Figure 5b shows the method for obtaining a strong specular component. A solid object (e.g., a metal strip) i s placed in front of the air bubbles. This permits inde- pendent adjustment of the specular and random reflection components over a reasonably wide range. It is essential that the bubble generators, transducers, specular reflec- tors and absorbing pads be carefully positioned to insure elimination of secondary reflection components. It has been found that the extraneous signal content in the sim- ulated channel can be made negligible (-60 dB or less).(’ A TYPICAL COMMUNICATION SYSTEM MODEL (figure 1) The communication system currently used in connection with the multipath simulator i s shown in figure 1. The transmitter has a crystal-controlled carrier frequency of 200 kHz. This carrier is single-sideband (SSB) modulated with a 4 kHz subcarrier. The resulting SSB signal is fed to the transmitting transducer, whence i t is radiated in the water. The receiving transducer picks up the signal re- flected from the air bubbles and other reflecting objects placed in intersection of the two transducer patterns. This signal is amplified and demodulated in the receiver. The receiver performs both envelope and product demodula- tion. The output from the envelope demodulator provides information about the fading of the envelope of the re- ceived signal. The output from the product demodulator i s used to extract information about the phase of the fading signal. Reference signals for the product demodulator and for the subcarrier phase comparison are obtained directly from the transmitter by means of cables. This results in one great additional advantage of using the multipath simulator rather than “the real thing.” Since the reference signals used at the receiver can be obtained directly from the transmitter, they do not have to be generated locally at the receiver. This eliminates a great source of uncer- tainty as to whether observed effects are due to the chan- nel behavior or due to time-, frequency-, and phase-refer- ence errors at the receiver. I -Iov TRANSDUCER - - Figure 4 -Transducer driving circuit TRANSDUCERS AIR BUBBLES SPECULAR Figure 5 -Two types of multipath channels: (a) pure random scattering, (b) random scattering plus strong specular Figure 6 -Amplitude record of the fading carrier envelope, pure random scattering 19 Statistical analyzer Relatively simple statistical analyzing equipment may be used to study many properties of a typical communica- tion model. Figure 7 shows block diagrams of the systems used for measuring amplitude distributions and binary (two-level) correlation functions. The design of these sys- tems was based upon the following characteristics of the received signals: a. Over a period of several hours, the statistical prop- erties of the received signals are essentially station- ary, thus permitting time-averaged measurements. b. Many of the signals for which auto- and cross-cor- relation measurements were desired are approxi- mately Gaussian with zero mean; this permits the results of simple binary (two-level) correlation meas- urements to be used to reconstruct the true analog correlation.G Two-level correlation techniques are also self-normalizing, ;.e., they yield the normalized cor- relation coefficient of the ac component of a Gaus- sian signal directly, so that precise monitoring of signal levels is not required during a test. c. Signal bandwidths of the order of 10 to 30 Hz permit the use of either continuous or sampled-data averag- ing techniques where desired. Amplitude distribution analyzer (see also reference 3, section 5-12) The system shown in figure 7a performs a continuous averaging of the output of a dual-slicer circuit to derive an estimate of the amplitude probability density function f(X), where f(X) = Prob (X - SX < x 5 X + SX) by measuring (l/AX) 3 Prob [ X - (AX/Z) < X < X + (AXlZ)]; AX small compared to the variance of X. The rate-of-change of the ramp X, and the output filter time constant, T = 10 C (T in seconds, C in pf), must be chosen for the particular process to be measured. In par- ticular we must choose K and C such that (for "low-pass" processes) : K = dX,/dt < < AX/T v/sec and where AX i s the total width of the slicer window = 0.2 v T = 10Cmr,j > > No cz l / f , T = 1OC i s the output filter time constant f,, = approximate bandwidth of the process (;.e., N, the zero-crossing rate of x i s of the order x ( t ) in Hz. of 1 /fo) In our case, f,, i s of the order of 10 Hz. Successful distribu- tion plots were made with C = 2 kif, T = 20 sec. The ramp rate was kept small compared to AX/T = 0.05; typically K = 0.005 v/sec. Faster sweep rates cause excessive dis- tortion of the plot due to filter time lag. Wider output filter bandwidth causes the "noise" in the plot to be exces- sive, due to inadequate averaging time. The input process should be scaled so that its rms value is about 3 volts, and its mean i s close enough to zero so that the range of Iyv COMPARATORS n V(f1 ~ VOLTAGE-TIME 0 1 s COUNtERS CONVERTER COINCIDENCES C A - B- A- B- CLAMP LOW-PASS FILTER Part of distribution analyzer Figure 7 - Block diagrams of statistical measuring systems: (a) amplitude distribution analyzer, (b) sampled-data binary correlator, (c) binary cross-power estimator 20 the process is within t l o v range of the sweep voltage. For Gaussian- and Rayleigh-distributed signals this is straightforward. A complete plot typically requires 200/ 0.005 = 4000 seconds (1 hr, 15 min)! This demonstrates the need for good stationarity of the channel parameters and the advantages of being able to simulate a channel on as fast a time scale as possible. This type of distribu- tion measurement proved suitable for our case, but would be cumbersome, if the fading rates were appreciably slower. Binary correlator (figure 7b; see also reference 5 and reference 3, section 6-5) The binary (or polarity-coincidence) correlator i s suit- able for making estimate of the auto- and cross-correla- tion functions of zero-mean Gaussian stationary random processes. I t was useful in our case for studying the phase components of the receiver signal, but would not be valid for performing correlation analysis of envelope signals (which may nevertheless be studied with a low-frequency spectrum analyzer). The binary correlator yields an estimate of the two-level or one-bit correlation function p S y ( s ) = € [sgnx(t l)sgny(tz)]=-(Cni-~); ~ = t : ! - t l binary N where n i= 1 i f x(tl) and y(t2) have the same polarity on the ith sample. It may be shown that, i f x(t) and y(t) are zero-mean Gaussian processes 2 Again, considerable time is required for measuring a cor- relation function, since at least 2000 samples must be taken for each value of T. In our case, T ranged from 5 milliseconds to 0.1 second. If the actual unnormalized correlation function is desired, one must dlso make care- ful measurements of the mean and rms values of X(t) and Y ( t ) during the measurement period; then one can estimate the correlation function by Rz,,(T) = XdcYdc f XrmsYrnispJu(T) RllnlOg Cross-power measurement (figure 7c) In many cases, we are interested in only p,.,(O), and an analog averaging method may be used in place of the sampled-data method used in the correlator above. Here the output i s related to 2 pZv (T = 0) = - arc sin p(0) binary 7r analog Although these simple hybrid statistical analysis systems used in the initial studies proved satisfactory for studying many basic channel properties, faster, more accurate, and more sophisticated measurements could be made with a small general-purpose digital computer and analogldig- ita1 converter interface. Faster-than-real-time processing of channel output signals could be accomplished by using a precision instrumentation tape recorder with servo speed control to record the signals and a reference carrier for playback at a faster tape speed. CONCLUSIONS A multipath simulator has been described that is readily constructed and flexible in operation. The multipath char- acteristics of the channel can be varied over a wide range of conditions, allowing simulation of nearly all desired types of multipath channels. Since the transmitter and receiver are located close to- gether, reference and synchronization signals required at the receiver can, i f desired, be obtained by cables directly from the transmitter. Difficulties with the local reference signals can thus be avoided, allowing a more exact investi- gation of the effects of multipath conditions on the trans- mitted signal and on the operation of the receiver. AC K N 0 W L E DG M E NTS The authors wish to express their appreciation to Dean T. L. Martin and Dr. J. L. Hummer, CENESYS Director, for providing the facilities used in this project. Thanks must also go to Mr. W. R. Nyren for his invaluable assistance in the equipment design and construction. Mssrs. E. J . Claire, L. Lerner, J. G. Stoides, and K. W. Dunipace also assisted in performing the experimental work. REFERENCES 1 H E GULLSTAD W K ROBERTS A radio propagation simulator using radio-frequency acoustic waves in a liquid FCC Laboratory Division Project No 32801 May 18 1965 A multipath simulator for use in evhat ion of spacecraft ranging and communication systems Proceedings Third Space Congress Cocoa Beach Florida March 1966 Random-process simulation and measurement McGraw-Hill New York 1966 information transmission modulation and noise McGraw-Hill New York 1959 Two-level correlation on an analog computer Transactions IRE/PGEC Vol EC-10 No 4 pp 752-758 Dec 1961 (Also Aug 1962) 6 E J CLAIRE L LERNER D M NEWLANDS J G STOIDES A system analysis of the CENESYS multipath simulator utilizing a receiver with a unique phase-locked loop design Unpublished Laboratory Report University of Florida GENESYS April 18 1966 Electronic analog and hybrid computers McCraw-Hill New York 1964 2 AMMANDERS 3 C A K O R N 4 MSCHWARTZ 5 CLBECKER J V W A I T 7 C A K O R N T M K O R N 21 Solution of optimal control problems on a high-speed RICHARD MAYBACH grew up in the paper-mill town of Camas, Washington on the lower Columbia River. From there he went south to Corvallis, Oregon and a BS degree in electrical engineer- ing from Oregon State in 1959. Then, ignorant of the effects of thermal shock on physical bodies, he moved to Tucson, Arizona to enroll in graduate school. I t was during this time that he was introduced to Dr. G. A. Korn, who said, ”Glad to know you; here is your project.” Nothing was seen of Dick for several days while he attempted to find out: (1) What i5 a servo multiplier? (2) How is the thing on this chassis (purportedly a wrvo multiplicr) sup- posed to work? (3) Why doesn’t i t ? Presumahly he found out, for he received his MS degree in 1961. Dick then entered the Army Signal Corps and was assigned to the research and development lab a t Fort Monmouth. As project officer he worked on a contract to develop input/output equip- ment compatible with the Army’s FlELData family of computers. The time was spent designing digital pattern generators and run- ning operational and environmental tests on thr delivered rquip- ment. He learned two very valuable things there-logic design and that everything fails in the humidity chcimlier; 134°F. and 99’/0 humidity will corrode even those shiny gold 2nd Lt’r. bars. In 1963 he returned to Arizona to find that the Analog Com- puter Lab had become the Analog/Hyhrid Computer Lab. It was back to logic design, but a t least thp debugging could he done in air-conditioned comfort. During this time he has been involved in a number of logic and circuit design projects, including sornc of the subsystems of ASTRAC II. Some of his current work is described i n this paper, which forms a portion of his PhD dissertation. Mr. Maybach is a member of SCi, IEEE, Tau Beta Pi, Eta Kappa Nu, and Sigma Xi. EDITOR’S NOTE Since the opening of the Computers in education section last May, al l the articles published have been written either by educators or established professionals in the field. The gist of most of these articles has been the use of analog or digital computers as teaching aids and as problem-solvind tools, and the emphasis has been on undergraduate work. Now the time has come to have a look at graduate use of analog and hybr id equipment, and since the student, rather than the professor or machine, i s the star in this show, w e present here an article showing what can be done by a student. Such work i s an outstanding example of the payoff that can be expected from initiating undergraduate stu- dents to analog and hybrid computers. ACS hybrid computer SUMMARY This paper presents a method for finding the solutions to minimum-time optimal control problems. The procedure is to implement Pontryagin’s Maximum Principle on an iterative hybrid rornputer. The state and adjoint equations as well as the control law are simulated using conven- tional analog components. The troublesome two-point boundary-value problem, which is always associated with Maximum Principle, is solved by iteration, using a digital parameter optimizer. Thus, a manual trial-and-error search for the proper initial values of the adjoint variables is un- necessary. W e show t h a t , for a large class of systems, it is not neressary to generate the Hamiltonian, because the neces- cary rondi t ion that i t normally must satisfy is redundant. This allows many problems to be greatly simplified. W e also presrnt an optimizing routine that solves the boun- dary-value problem. This permits the proposed method to he used on any hybrid computer that incorporates a ,cencral-purpose digital computer. The solutions to two problems show that the proposed method is feasible Average convergence times ranae from less than one .second to about 70 seconds. These vary with the initial conditions on the state variables. The examples were solved using ASJRAC I / , a small (40 amplifier), high speed (up to 7000 solutions per second), iterative hybrid computer w i th only modest component accuracy (0.25 per cent). AlthouFh the discussion and examples are limited to a minimum-t ime performance index, the method is easily rxtended to cover other criteria. 22 1. PONTRYACIN'S MAXIMUM PRINCIPLE' Consider a dynamical system whose state i s governed by n state equations dxi . ~- = xi = fi(X1, x2, * * ' , x,, u1, uj, a - * , u,.) dt where the x, are state variables, and the uj, controls. Ad- missible u j are bounded, piecewise-continuous functions of time. In this paper we will consider only cases in which both the initial state, x(0) = [xl(O), xzlo), . . -, xn(0)], and final state, x(T) = [xl(T), xs(T), * * e , x,(T)] are given. We will further restrict ourselves to consideration of cases in which we desire to move the system from its given initial state to its given final state in such a way that the time, T, i s minimum. Define the n + 1 adjoint equations as where the pi are adjoint variables. Also define the Hamil- tonian as " (1.3) j=1 Note that this i s valid only for the minimum-time case. The Maximum Principle is, of course, applicable to a much wider range of problems. It i s now possible to state Pontryagin's Maximum Prin- ciple. Let uj( t ) , j = 1, 2, * * , n, be an admissible set of controls which transfers the state from its initial position, x(O), to the final position, x(T), and let xc(t), i = I , 2, * * , n be the corresponding trajectory. In order that the uj(t) and xi!() yield the optimal solution to the problem, it i s necessary that there exist nonzero continuous functions pi(t), i = 1 , 2, - e , n, corresponding to the xi(t) and uj(t) such that: 1 . For every t, 0 5 t 5 T, the function H of the variables uj attain i t s maximum (with respect to the uj) at the point uj = uj( t ) ; 2. At the terminal time, T, the relations po(T) _< 0, max H(T) (with respect to u,) 5 H*(T) = 0 are satisfied. This principle provides only the necessary conditions for a minimum time, T. It will single out from the con- tinuum of trajectories joining the given initial and final states, isolated candidates for the optimum. Hopefully this number will be small. The Maximum Principle i s appli- cable only to systems where: 1 . fi, i3fi/i3xj, i, j = 1 , 2 , e , n are defined and continuous; 2. uj( t ) , j = I , 2, . . e , r are bounded piecewise-continuous functions. 2. A SIMPLIFICATION THEOREM If a system can be described by equations of the form c = a d x ) + bij(x)u,, i = 1 , 2 , * * -, n, (2.1) 1-1 where the controls, ui, are subject to the constraints I u j I j L j , j = 1 , 2 ; . - , r , (2.2) the functions ai are such that &(XI, x21, * . *, xnf) = 0, i = 1 , 2 , * , n, (2.3) and the state i s to be moved from a given initial state, ~ ( 0 ) = Xn, defined by x1(0) = Xin, x J O ) = x20, ., xn(0) = X,n to a given final state, x(T) = XI, defined by xt(T) = XII, xz(T) = XZI, * * * , x,(T) = xn~, in minimum time, T, then the condition that H*(T) = 0 i s redundant. Proof: From equations (1.11, (1.31, and (2.11, H i s maximized with respect to the uj, due to equation (2.21, if j-- 1 L i- 1 J i=l The only condition on po i s that po(T) 5 0. This i s satis- fied if then c (2.5) I f the boundary condition x(T) = XI i s satisfied, aiCx(J)I = 0 and H*(T) = 0, regardless of the values of the pi(T). Thus the theorem is proved. 23 There are now 2n equations, n state equations and n adjoint equations, in the system. There are also 2n bound- ary conditions, the n given initial and the n final values for the state variables. The n initial conditions can be di- rectly set, but the n final conditions must be satisfied by properly adjusting the n initial values of the adjoint var- iables and the time, T . Clearly one of these adjustments must be redundant. Note that nothing in the above has affected the adjoint equations (1.2). I f p1, pz, . ., p,, i s a solution, so is Apl, Apz, * * , Ap, for any constant A. We can thus arbitrarily fix the magnitude of the initial value of one of the adjoint variables. However, the signs of al l the pi are important due to (2.4). We have reduced the boundary-value problem from one involving an (n + 1)- dimensional search (over p1(0), p2(0) , - -, p.(O), T ) to one involving only an n-dimensional search plus a binary de- cision. All this is of no great theoretical interest, but i t results in a considerable saving in computer setup complexity. First, i t is no longer necessary even to generate the Ham- iltonian, much less enforce any boundary condition on it. Furthermore, by reducing the dimension of the search, a significant improvement i s made in the convergence of the boundary-value enforcement process. 3. THE COMPUTER The ASTRAC II system i s used in the configuration shown in figure 1. The state and adjoint equations are simulated on high-speed analog elements at solution rates of up to 1000 per second. During the optimization process (search for the correct values of the adjustable parameters), the analog simulation generates a value of a criterion function for each set of trial parameter values. The criterion func- tion is f(t) = - ai 1 xi(t) - xtf 1 (3.1 1 where the a, are weighting factors, and the xi!, the given final conditions. The optimizer searches for sets of values of the adjustable parameters that maximize f (T ) , the final value of f ( t ) . Note that the maximum value i s zero, and that when this is attained, the boundary-value problem i s solved. After the optimization process has converged, the analog portion will generate and display the optimal tra- jectory and control. 2 I = 1 _. - ~ ___ Adjuslable paramelerr ( ~ ~ ( 0 ) . '", p.(0), J) Criterion Analog simulation fun< til,n (state and 1 adjoint equations) 1 I criterion funrtion) I 1 t t I I Figure 1 -Simulation of Maximum Principle on ASTRAC II The parameter optimizer's' search for the maximum value of f (T) i s made by performing a modified random walk with the values of up to four parameters. The initial value of the step size, A, i s 10 volts, and the dynamic range is 5 1 0 volts. The value of each parameter i s per- turbed by one of the values +A, 0, or -A, which are selected at random. The (boundary value) criterion func- tion, f (T ) , i s then computed for the new parameter values. If f (T ) i s larger than f,,,,, the largest value previously ob- tained, then the trial is termed a success, and the per- turbed parameter values become the operating point for the next perturbation. On the other hand, if f (T) < fma,, the trial has failed. In this case the unsuccessful perturba- tions are discarded, and the parameters return to their previous values for the next perturbation. This perturb-test procedure continues until a number of consecutive failures result. The step size, A, then halved, and the process continues until A reaches its smallest value (about 80mv). Here a test is made to determine if the process has converged to a local maximum. The true maximum i s known to be zero, and i f f,,,, i s significantly less than this, the whole process starts anew with A = 10 volts. The internal operation of the optimizer i s best described by flow diagrams, figures 2 and 3 . There are two ways in which the computer can enter the optimization routine from analog computation. At time t = T, f (T) has been formed, and the success-failure test is made. If however, a computing element overloads prior to this time, compu- tation ceases, and the trial i s judged a failure. If the trial is a success [ f ( T ) > f,,,], the sequence of operations proceeds as on the right of figure 2. The suc- cess counter i s advanced, the failure counter reset (only consecutive events are counted), and f,,,,,, becomes the present value of f (T ) . I f the number of successes, nn, has reached a preset number, Ns, the step size, A, i s doubled. A i s stored as a single "1" in an eight-bit shift register. Thus "shift left" i s equivalent to "double A." This ability to increase the step size was found to have no significant effect in the examples discussed in this paper. If the trial is a failure, things are more complex. First the unsuccessful perturbations are removed. The failure counter is advanced, and the success counter reset. If the process has not yet converged (A > A,,,,), A i s halved when nY, the consecutive number of failures, reaches the (preset) number NP. I f the process has con- verged, f,,,,,, i s tested to see i f i t is a local maximum. The largest possible value of f ( T ) i s zero. If f, , , , , , i s less than a preset number F ( F < O ) , i t fails the local maximum test. After N,,, consecutive failures, a l l parameter values are reset, A i s made large, f,,,,,, made small, and the maxi- mization process starts anew. The lower right portion of the flow diagram sets f, = f ( T ) after NP consecutive failures i f the process has con- verged to the global maximum. f,,,., is scored in an analog sample-hold circuit which, of course, is subject to drift. This periodic resetting prevents any drift from causing large errors in the value f,,,,. By allowing the optimizer to con- tinue its local search after convergence, we enable i t to 24 track a slowly moving maximum. This might arise due to a time-varying system or to slowly changing initial state values. Figure 3 shows the process of actually perturbing the parameters, ai. A digital noise generator (3) is stepped to develop a random word, which in turn generates the per- turbation 8, . SI may have one of three values, +A, 0, or -A. This value is stored, and the process repeated for 62, Sa, and S4. The optimizer contains a provision for correlat- ing the Si with the success of the previous run. That is, altering the probabilities so that the perturbations, ai , tend to move the ai in the same direction as in the preceding run i f i t was successful, but in the opposite direction as in the preceding run i f i t was a failure. This feature was not found useful in this study. After a l l the 8, and ai have been developed, the com- puter again enters its analog computation phase to compute the resulting f(n. P computation I '7' Step noise generator to form +. 0, or- Index \UCCEss uiunter K r w t f.iilure uiunter Slorr n rw I , . , , , , C r i n w i i t ivr \U( r m s l r q l Form 6, from the noi5e generator Step NC + success nx = 0 counter + Step NC + C-nnrrrul ive f ,i i lure IC\t I I f Local maximum test -+ n+ - NI Step NG L-r' Krwt I , , , : , , alter NI conwcut ive l,i I Iu res with A 7 A,,.,,, and I , , , , , , > r nr = nlr + 1 k4 Consecutive local maximum test store SI Perturb a l l 4 parameters + I nt = O 'ioptimization process Reaet local maximum rounter Figure 2 - Optimizer flow diagram, determination of step size Figure 3 - Optimizer flow diagram, parameter perturbation 25 4. SECOND-ORDER EXAMPLE Consider the system 2 = u, ju( 5 1, X(T) = x(T) = 0 with a minimum-time performance index. Identify XI = x and x2 = 2. Then X I = x2, x2 = u (state equations) (4.1) H = Po + PlXZ + P2U (Ham i I ton i an) (4.2) p o = 0, P I = 0, p z = --p1 (adjoint equations) (4.3) f ( t ) = -Q,IX1 ( t ) l -wlxdt) l (criterion function) (4.5) The considerations of section 2 apply here, and we can let P I = -+I. (4.6) The problem now i s to find the values of pZ(0) and T and the sign of p1 that cause x l ( T ) = x z ( T ) = 0. The analog simulation i s shown in figure 4.4 All integrators are con- trolled by the signal R” (R” = 1 implies reset). Electronic switch number 1 causes lop1 to be +IO volts or -10 volts, depending on the most significant bit of the optimizer’s parameter al. Digital-to-analog converter number 2-11 converts the parameter a. (an eight-bit digital word) to the analog signal ~ ~ ( 0 ) . The control, u, i s developed by com- parator number 6 followed by a precision diode-bridge u = sign (p.) (control law) (4.4) P’ 7 ’D 511 T i s - - -10’ + WI, l4 0 4 No1c.s’ All inttyyator &ins = 20.000 -Denotes digital input Figure 4-Simulation of second-order example limiter. The limiting level is accurately adjusted to = *I volt with pot number 13. Figure 5 shows the conversion circuits needed to present the results of a trial to the optimizer, as well as the circuit that generates R”. Integrator number 23 i s controlled by R , which is a logical 0 for 1 msec, then a logical 1 for 1 msec ‘ind repeat. The output of this integrator i s a -10 to + I O volt ramp. Parameter a, then determines the time at which the output of comparator number 4-22 undergoes a posi- tive transition and hence the time interval for which R”= 0 (compute). Thus becomes the time T . The_ signals R and V are combined in NAND gate number 18. R holds the integrators in reset while integrator number 23 i s reset. V holds them In reset after an overload develops. This signal 15 generated b y the optimi/er from the signal m. 15 normally a logical one. Some fixed time prior to time I = 0, i t moves to zero, thus placing track- hold number 28 in track. This i s necessary as the operation of the sample-holds becomes errat< i f their track periods are too short. Just after time I = 0, 5:! becomes a one, thus returning the control of the sample-hold to R”. Sample- hold number 28 moves from track to hold a t time T , storing / ( T I . f ( T ) i s compared to f,,,,, by comparator number 5-30. The signal (failure) 3-20 for overload -10 dR Figure 5-Conversion circuits 26 The output F informs the optimizer of :he success or failure of the run. If the run was successful, the optimizer forms L = 1, M = 1 which causes f, = f(n. The combination L = 0, M = 1 is used to set fmax = -10 (section 31, The signal S1 causes sample-hold number 19 to store the value of f ( t ) at t=0. This permits E to be adaptive. As xl(0) and xZ(0) become larger, so does T*, the optimum T. As T* becomes larger, f(T) becomes more sensitive to small changes in the parameters, Thus e must also increase to prevent the resulting jitter in f(J) from being interpreted as a local maximum. The contour of f (T ) for the initial condition xl(0) = 0, xAO) = 5 is shown in figure 6 . The true maximum is located T,seconds 0 2 4 6 8 10 12 14 16 18 20 Figure 6-Contour of f (T) for xl(0) = 0, x2(0) = 5 at J = 12 seconds, pz(0) = -8.4. The only effect of pz(0) i s to alter the time, t,, at which the control changes sign. t., i s located on a straight line connecting the origin and point (IO, -10). To the left of this line, f(T) i s independent from the value of pz(0). Note the local maxima, T = 0 and T = 5, -10 5 pz(0) 2 -5. Because of these, a hill-climbing technique is not assured of success. However, since the value of the true maximum is known, convergence to a local maximum is easily determined. A hill-climbing tech- nique with a random starting point and a local maximum rejection feature will eventually succeed. Figure 7 shows a phase-plane display of the response to the initial condition xl(0) = 0, xz(0) = 5. 0.5~1 is displayed horizontally and x2 i s displayed vertically, both at 2 volts/ cm. The search is shown continuing at the smallest step size (about 80 mv). Note the sensitivity of the final values to small changes in the initial conditions of the adjoint variables. Figure 8 shows the time-response to the same initial condition. The top trace is 0 . 5 ~ at 5 volts/cm, the middle is x p at 5 volts/cm, and the bottom one is 5u at 10 volts/cm. Real time i s 2 seconds/cm, and computer time is 0.1 msedcm. Figure 7 Figure 8 27 Table I compares measured and theoretical response times for two different iteration rates. For these data the optimizer was disconnected, and pi, p2(0), and T were set by hand. Table I-Comparlson of theoretical and measured response times 3.11 636 2.64 s.6a 246 4,% 2.00 4.00 1.40 2.84 Table II shows average convergence times for various initial conditions. Table Il-Average convergence times 4 0 12.3 6 0 22.6 6 0 4.7 w 0 3.1 ~ ~ a m + a w o ,hl .36 Nr*M iRr*lrm awragal over 10 to 20 trials. Number of iterations 400 1000 17% 35,100 14,000 4950 61 543 .t1m 23543 15543 5. THIRD-ORDER EXAMPLE Consider the system again with a minimum time performance index. Let XI= x, x2 = x, and x3 = i , then XI = x2, x2 = xs, i3 =u (5.1) H = po + plx2 + ~ 2 x 3 + psu (5.2) p, = 0, p1 = 0, p2 = -pl (adjoint equations) (5.3) p s = -p2 u=sgn (pd (control law) (5.4) f ( t ) = -a l lx l ( t ) l - a 2 1 x 4 -aa I ~ 3 ( t ) I ... x = u, I u I = 1, X(T) = i ( T ) = x(T) = 0 (state equations) (Hamiltonian) (criterion function) (5.5) The considerations of section 2 also apply here. The simu- lation is shown in figure 9, and the comments of figure 4 apply. The simulation-to-optimizer conversion i s identical to that of the second-order case, shown in figure 5, except that there are four more diodes associated with compa- rator number 3-20 to detect overloads of x3 and p3. Time responses for two different initial conditions are shown in +10 - -10 d -101 Figure 9-Simulation of third-order example 28 figures 10 and 11. The traces from the top are 0.04x1,0.2~2, xs, and 5u. The top three are at 2 volts/cm, and the bottom i s at 10 volts/cm. The real time scale i s 2 sec/cm, and com- puter time i s 0.1 msedcm. Average convergence times for the initial condition xl(0) = 50, xZ(0) = xs(0) = 0 is 24.6 seconds (12,300 iterations). Any large change of these values requires rescaling of the adjoint variables. The problem here is that f(T) is very sensitive to small changes in the initial conditions of the adjoint variables. This condition i s so extreme that i t is very difficult to distinguish local maxima. An eight-bit word just does not offer a sufficiently small minimum step size. ACKNOWLEDGMENT The work described in this paper i s part of a continuing hybrid analog-digital computer study directed by Professor G. A. Korn. The writer is very grateful to Professor Korn for his suggestion of the topic and for his guidance on the work; to the General Electric Company for fellowship support; and to Doctors Howard S. Coleman, Dean of En- gineering, and Roy H. Mattson, Head, Electrical Engineer- ing Department for their encouragement and contribution of the facilities of the University of Arizona. The ASTRAC II hybrid computer used in this study was developed under the joint sponsorship of the National Aeronautics and Space Administration and the United States Air Force Office of Scientific Research. 6. CONCLUDING REMARKS The above experiments have shown that this method of solving optimal control problems is feasible. There are three major problems to be solved before it can be re- garded as practical. The sensitivity of the solutions to the initial values of the adjoint variables requires that the latter be adjustable with a high resolution. The eight-bit word length used for these experiments must be increased. Also, table II indicates that the present optimization strategy is inefficient. In addition to these practical problems, there i s an un- resolved theoretical difficulty. Pontryagin's Maximum Prin- ciple states that of the u(t) that move the state of the system SO as to satisfy the given boundary conditions, we want to choose those that maximize H. Our proposed method does not solve this problem. We state that of the u(t) that maxi- mize H, we want to choose those that move the state so as to satisfy the given boundary conditions. As far as the author knows, these two problems have not been shown to be equivalent. In section 3, we noted that even after the process has converged to the optimal solution, we allow the optimizer to continue a local search. As a result, one can slowly vary an initial condition or a parameter of the system and con- tinuously observe the effects of this change on the opti- mum solution. The rapport between the problem and the investigator that has always been of such value in analog simulation is now available in optimal control studies. The advantages of this are difficult to exaggerate. Fi f REFERENCES PONTRYACIN et a l The mathematical theory of optimal processes Translated by K N Trirogoff Interscience Publishers New York 1962 B A MITCHELL A hybrid analog-digital parameter optimizer for ASTRAC / I Proceedings 1964 Spring Joint Computer Conference SIMULATION vo l4 no 6 June 1965 pp 399-411 R L T HAMPTON A hybrid analog-digital pseudo-random noise generator Proceedings 1964 Spring Joint Computer Conference SIMULATION vol 4 no 3 March 1965 pp 179-187 Report Uniform graphics for SIMULATION SIMULATION vo l6 no 3 March 1966 pp 137-140 lgul ?gut re 1 IO 'e 11 29 R.L. Maybarh : Generation of iniierse functions GENERATION OF INVERSE FUNCTIONS BY THE METHOD OF STEEPEST DESCENT * by R.L. MAYBACH ** ABSTRACT. - The technique of steepest descent can be used to generate the in- verse of a function with standard analog or hybrid computer components. The resulting system is often free from the instability problems that plague inverse function generation by implicit computation. When the method is applied to forming division from multipli- cation a four-quadrant divider results. Neither of the two most common penalty functions, error squared and absolute error produce wholly satisfactory operation. If the loop gain is allowed to increase without bound, it causes relay or bang-ban8 type of performance that is free from the objectionable response of the previous systems. Because of their cost, relatively few special purpose function generators, usually multipliers, and sine and cosine generators, are available on most analog com- puter patchbays. All other functions must be labor- iously set up on general purpose diode function generators. Even if the diode function generator is of the programmable type, the available number of prog- rams is limited. It is worthwhile then to investigate methods of generating inverse functions [ y = f - I ( x ) ] from the function itself [ x = f (y)]. This will provide division, square root, arcsine, and arccosine from avail- able special purpose function generators. The generation of inverse functions can be accom- plished by ,the use of a function generator in an amplifier feedback loop (fig. 1) [ I ] . This system U I Fig. 1. - Generation of inverse Functions by implicit computations. I - 2 /1 u Fig. 2 . -- Block Diagram for System 1, "7 1 I- $. = y2 (-- + X)' LOO often exhibits high-frequency oscillation due to the phase shi,fts of the amplifier and function generator. Instability is especially likely if the function generator is of the carrier type, for example, a time-division or triangle-integration multiplier. Devices such as these often use sharp cutoff, high phase-shift filters to * Manuscript recrived October 17th 1965 ** University of Arizona, Department of Electrical Engincc- ring. maximize bandwidth. It is not possifile to obtain the inverse by this means if the function generator is sufficiently perverse. This problem alone is serious enough to justify more complex methdds of generating invene functions. Methods of Steepest Descent. Consider a cost function 4 = 9 (XI , ..., x,,). This may be minimized with respect to eakh x , by forcing i , = -K @ + / a x , ) 11, 2) . The speed of response is clearly proportional to K. This method has the limitation that 4 must have no local hinima. Fortun- ately such + can often be found whCn this technique is applied to generating inverse funCcion. Suppose we wish to generate y = f 1 (x) given .Y = f (y). Two cost functions havd &en suggested, +, = - rhese can be minimized if f ( y ) idcreases monoton- ically with y. If y can be varied to reduce 4 to zero, then the desired inverse has been folind, since t$ = 0 is true only if y = f-1 ( x ) . The resldting expressions for jt are : 1 2 I. - f (y) l ' and 9 2 = 1 % - fb)l 1'1. 1 2 Y = K lx - f (r)l @ f l a y ) if 9 = - [x - f(r)l'* j = K sign [x - f ( y ) ] @ f l a y ) if Q = 1 % - f (Y) I * Since f ( y ) is known a f p y can be geberated explicitly. As K is increased the response t ihe will decrease. The dynamic characteristics will be most favorable if K can be made large. But if j beccmes too large the inteKrator that is attempting to gat ra te will over- load. Thus, we wish to let K + stmint that 1y1 < A (constant). If we apply this to the above we find that j = K sign @ f l a y ) sign [k - f WJ The same relation results from either t$. This is interesting for two reasons. T h C system is always driving at full speed toward the minimum. The indicatd multiplication of sign finctions can be per- formed digitally by an exclusive br rather than by an expensive analog multiplier. un i er the con- 30 - - - -~ -~ _ _ _ _ _ Annales de /Association internationale pour le Calcul analogipe TO find the possible advantages of each scheme, the 3 systems above were applied to the problem of generating z = - 100 (x/y) from x = - ( 1 / 1 0 0 ) yz. This has the interesting additional property that the result is a four-quadrant divider which is stable for x =, y = 0. In this case z = -K (x + X ) (y / lW). The 100 computer set-up for this is shown in figure 2. The gains shown result in a stable system and allow x to undergo a 40 volt step without causing the summer to overload. Larger steps could, of course, be accom- modated (at the expense of risetime) if the summer's gain were reduced. The static accuracy is essentially that of the multipliers, and the dynamic characteristics are shown in figure 3. Fig. 3. - Transient Response of System 1, YZ 100 Q = y2 (-- + X)' Although the response times are independent of x , they do vary wi,th y, and below 50 volts the system becomes relatively sluggish. Also, the scheme requires 2 expensive multipliers instead of the one required by most dividing schemes. Systeiii 2. + = (yz/100) + x . For this case i = -K(y/lW) sign (2 + x) . One of the multipliers of system 1 is replaced by a comparator and a switch. This is much cheaper, especially since the switch need not be particularly accurate. The resulting computer diagram is shown in figure 4. 1 0 0 The static accuracy of this system is again essen- tially that of the multiplier. The dynamic response is markedly different from that of system 1 . Instead of resembling a linear second-order system, the step response is a ramp with slope proportional to y. The Fig. 4. - Block Diagram for System 2, 1 2 slope is approximately - y volts/millisecond. The 0-100 percent rise-time shown in figure 5 is roughly comparable to the 2 percent settling time of figure 3. Cornparison of these two figures shows that system 2 has the same sluggish response at low values of y that troubles 1. Systeiiz 3 . K + CI). YZ 100 Define two binary variables U+ and U,. For this case z = -A sign (-- + x ) sign (y). U+ = sign ( yz + x ) , U, = sign ( y ) . - 100 Then in Boolean algebra notation - - z = -A z = + A if Ug . U, + U+ . U, = 0, if Ug . U, -+ Ug . U, = 1. - I The resulting system is shown in figure 6 . The step response of this system is a ramp with a slope of about 55 volts/millisecond. The 0-100 per- cent rise-time is shown in figure 7. Comparison of 4 In 0 E 0 i - 3 E i E z= .- c .E e x 0 2 T 0 1 0 31 R.L. Maybach : Generation of inverse functions ___ ~- ~. ____ __ - 20 40 60 80 100 X-Input step, Volts Fil;. 5 . - Tr.mcieiit Resp,mcc c r f System 2 . YZ I O 0 $I = (-- + X ) I I Fig. 6 . - Block Diagram for Systcin 3 , K -+ % figures 3, 5 , and 7 shows that system 3 has the most desirable transient response. Only system 3 is not sluggish at low values of y . Its static accuracy is again essentially that of the multiplier. It will be interesting to see the effect of an error in the multiplier. Suppose that .I = ( 1 / 1 0 0 ' ) yz 1- F . where E is the error. Then z = - 100 -- 4- 100 - Y Y .Y E .- i c In .- I._ L 2 s 0, 0 0 1 0 FiR. 7. - Transient Response of System 3, K ---* 00 The statement that the accuracy of the divider is the same as that of the multiplier is misleading. It would be more accurate to say that the error is multiplied by loO/y. This is true of any system that obtains division implicitly from multiplication and is not a special defect of steepest descent. Practical Considerations. Quarter-square multipliers and Philbrick USA 3 operational amplifiers are used in all of the systems. System 1 is straight-forward, and no unusual pre- cautions are necessary. The impedance level must be kept low, of course, in order to realize reasonably fast response. A detailed circuit diagram of system 2 is shown in f i p r e 8. Amplifier 1 forms a comparator with about & 0.6 volt levels. These are large enough to reliably operate the switch on the input to amplifier 4. A comparator with higher switching levels will also serve, but it will introduce excessive noise into the input. This is because in the steady-state the comparator switches rapidly between its 2 levels and some feed- through is inevitable with the simple switch used here. The 500-1000 pf trimmer on the comparator is needed to keep it stable. Note the use of speed-up capacitors on amplifier 2 , which could be replaced by a simple digital inverter. Annales de PAssociation intern&onala pour le Culcul anulogique 32 A detailed block of system 3 is shown in figure 9. This discussion of system 2 also applies here. The diade marked with an asterisk is not necessary logic- ally. Because of the low levels, however, there must be an equal number of diodes facing each way in a31 paths SO that the saturation voltages cancel. If the extra diode is removed, the comparator levels must be increased which will raise the noise level. REFERENCES { I ) Korn, G.A. and T.M. Korn : Electronic Andog and Hybrid Computers, McGraw-Hill, New York, 1964. 12) K e b , H.J. : Method of Gradients, in Leitmann. G., Op- timization Techniques with .4pplication to Aerospacs Sy.r- terns, Academic Press, New York, 1962. DIODES Si R ' s in M n Y Fig. 8. - Circuit Diagram of System 2, YZ 100 + = ( - - - + X ) 01 Fig. 9. - Circuit Diagram of System 3, h -+ m 33 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS FOLLOWER Performance of Operational Amplifiers With Electronic Mode Switching* G. A. RORNt SummarpThe linear-circuit performance equation for M im- portant CtU of mods-ewitched operational amplieers io dadoed to identify erron caueed by Baite feedback loop gains, switch reris- taace, and follower-amplifier source impedance. Errora due to capuitor dielectric absorption, switching rpikes, dc leakage, and current limiting are d i m m e d with reference to an e lec trdcd ly witched integrator (urnpiehold or analog-memory circuit), and ruiour derign requirementr are lirted. INTRODUCTION LECTRONICALLY-SW ITCH ED operational arnplifiers of the type shown in Fig. 1 switch the input voltage and/or the mode of operation (transfer function) of an accurate operational amplifier with a single switch operated by associated analog coni- parators and/or digital circuits. The best-known exam- ples of such techniques are electronically controlled inte- grators or analog-memory (sample-hold) circuits' and single-pole double-throw switches in modern iterative analog computers and related hybrid analogldigital coniputing equipment (Fig. 2). The input impedances Moin Electronic Switch follovrr Amplifier xo Fig. 1. IN _ _ . IJ OUT I I - I t - Fig. 2. * Received July 27, 1962. t Department of Electrical Engiiieering, I'niversity of Arizona. Tucson, -Ark. qite1ii-y response, 1WI. 1 -1. Brubake? "Precision analog niemory has extended Ire- Elrrtmnirs, vol. xs, pp. 111 - I , & . < ; Septerrilwr 29, 21 and 2,' can be replaced by summing networks, and electronic commutators can be built with multiple switches.* When the electronic switch in Fig. 1 is OFF, the in- put X1 and the feedback inipedaiicw 21, 20 are essen- tially out of the circuit, which now functions as an ordinary operational amplifier with iiiput'X1'. When the electronic switch is ON, the low-impedance follower- amplifier circuit connects the input XI and effectively shorts the input and feedback current through 2: and Zo'. The earliest circuits of t h i s type eniployed simple cathode followers instead of the feedback aniplifier fol- lowers indicated in Fig. 1 ; more accurate unity-gain followers (high-gain difference amplifiers wi th unit feed- back) are now generally substituted to obtain reduced drift and lower output impedance. A notable advantage of the arrangement of Fig. 1 over other mode-switching circuits is tIi,it the input diode limiter prevents signal voltages .it the switch from ever exceeding five to ten volts, so that the elertroiiic switch can be operated directly from low-voltage off - the-shelf-digital-coniputer modules, arid low-vol tage high-performance switching diodes and transistors can be used. As an added advantage, the switch is driven by a low- impedance source and the main-amplifier summing point itself is maintained a t a low impeclance with re- spect to ground while the switch is ON. Both six-diode and six-transistor switches are used ; either type conibines shunt and series switching to pro- duce open-circuit transfer impedances in excess of 10" megohm a t dc, 2000 megohms a t 100 kc, and 20 megohms a t 1 Mc. Presently available switches, then, have almost negligible signal leakage; errors in the OFF condition are mainly due to iniperfectly cancelled switching spikes and dc leakage currents in diodes or transistors. L INEAR-CIRCUIT ANhi.ysis We shall leave the discussion of switch-iiiibnloiice effects until later and corisider the switch as on almost ideal switch wi th infinite bock resistance and forward resistance RON of the order of 20-100 ohms. The linear operation of our circuit is then described by the equiv- alent circuit of Fig. 1. If the unity-gain driver is a * 14. D. Huskey and G, .A. Korii, "Ci)rnputer llalidbook," blc- Graw-Hill Book Co., Inc., Sew York, S. Y . ; 1962. Korn: Operational Amplifier8 with Electronic Mode Switching 34 high-gain feedback atnplifier, a will be very close to one, is the forward gain from the follower-amplifier input to and the internal impedance Z s of the follower aniplifier the output of tlie iiiaiii iiniplifier. I f we consider - can be of the order of 10-*-10 ohms a t dc and 100-1OOO ohms at 100 kc. Amplifier input impedances 20 and Za' have been included to allow lor input capacitances and input conductances, especially in the case of transistor circuits. When the switch is OFF, its transfer impedance is, as noted before, practically infinite, so that we have an operational-amplifier circuit with the well-known per- formance equation ,2 A & i m zu' 1 - ABOFF ZI' xo = - -X1' -- 1-7,- ?L',', 1 - Zu'h 1 ac3od1 1 - AoN&" I Zs + RON I where is the feedback ratio with the switch OFF. When the switch is ON, its transfer impedance is es- sentially a resistance R O N between 10 and 100 ohms, and we have zo'( a xo = 1 - AB1 Zs + RON where is the feedback ratio reducing the gain of the main amplifier; 2 s is follower-amplifier source impedance, and where ( 3 4 is the feedback ratio for the follower-amplifier input. ance equation in the switch-ON mode, Combining (2) and (3), we find the desired perform- 1 where ail 1 - A191 A O N = ( 4 4 Discc S S I ~ N Eqs. (4-6) indicate tlie importance of sninll Zs +&N for accurate performance. K f l N will be between 10 and 100 ohms. The follower-amplitier source illipedarlce Z s may var) between substantially less than 0.01 ohni at dc and a t most a hundred ohms a t 1 X I c l or high-quality solid-state follower amplifiers. I f 2s+K,ls is small com- pared to ZO', ZI', and Z o ' , (2b) ).ields (7) Z s 4- RON 8, _______. ZO' so that (6) reduces to Note that &, and hence Zs+K,,s , also affects A O N , so that reduction of 2~+/i,,N reduces both error ternis in (8). I n ali existing circuits of the type studied, the dc fol- lower-amplifier gain a(0) is approximately 1, mainly because larger values of a might cause instability. Even a conditionally stable main amplifier and/or follower amplifier will exhibit ringing after each switching opera- tion. Note also that, i n the usual feedback-type follower circuits, any increase i n a implies ;L proportional increase in the source impedance 2 s which should, if a t all pos- sible, be only a fraction of the switch resistance RON. EFFECTS OF PARASITIC MPE:DAN(:ES. C.\PXITOR DIELECTRIC ABSORPTION The effects of various nonideal coiiiputing impedances 011 operational-amplifier performance are discussed in detail by Single.2 Noninductively-wound wirewound resistors can be used in suninling aiiiplifiers (and hence also as initial-condition resistors in switched integra- tors) operating below l \IC, since their small remaining parasitic inductance is tuned out by the distributed capacitance. I t is recommended that such resistors paralleled with 10-50 pf capacitors to improve frequency response and st:ibility.2 Integrator input resistors, on 3> IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS the other hand, should have as little parallel capacitance as possible, so that film resistors are preferable for use in wideband repetitive analog computers. To reduce phase shift due to resistor and sitmniing-point capacitances a t frequencies above a few kilocycles, it is almost nian- datory to employ feedback arid sumniing resistances below 10 kc, so that the use of high-current transitor amplifiers is recommended. N’hile resistive capacitor leakage is usually negligible, capacitor dielectric absorption in high-quality poly- styrene and tefloii integrating or storage capacitors (D < 2 X lo-‘) will cause phase-shift and storage errors of the order of a few hundredths of one per cent for ordinary computing and holding times.* To visualize the effect of dielectric absorption 011, sa)., ii switched integrator (Fig. Z), imagine one or niore series K C cir- cuits across the niain capacitance C. I f the latter has been discharged lor sonie time a:id is then quickly charged to a voltage E and placed into I-IOLD, the parasitic RC circuits will draw “relaxation” currents until their charges are equalized. Although errors due to capacitor dielectric absorption can he traced in a very accurate “slow” electronic aiialog cornputer, they will probably be masked by larger phase shift and switching errors i n present-day iterative conipirters. NONLINEAR EFFECTS: TRAC K-€101 Li ClR< CllTS In the TRACI. rcvluws the con t rol-curren t requirements. I n the author’s opinion there is, however, still much to be learned about the choice of switching circuits for sample-hold and other-niotie-switchilIg clevices; in par- ticular, the relative advantages of various diode aiitl traiisistor switches have not been conrlusively estnb- lished. I t appears certain, however, that even the brute- force method of employing high-current amplifiers ; ~ i i d switches to permit larger storage capacitances will en- sure memory and reset accuracy within 0.1 per cent of FS for iterative differential analyzers. It is, in fact, possible to use all-electronic mode switching i n “slow” electroiiic analog computers to obtain switching errors within 0.1 per cent of FS for a t least 50-sec coinputcs runs with 1 pj integrating capacitors.3 a G . A. tiorti. “ S e w high-speed annloK and :iiialc)g-digitiil corn- puling techniques: the r\SIHAC svstrill,” / ’ m i . . 3 r d ,I lCA C’onjfr- m c r , Opatija, Yugosliivia, Septcinher, 1961 ; t’rcsxs ;lc.;i&inic~ties Europcfeiines, Brussels, Belgitini; 1962.

Progress of analog-hybrid computation

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