Surface flashover of oil-immersed dielectric materials in uniform and non-uniform fields

The applied electrical fields required to initiate surface flashover of different types of dielectric material immersed in insulating oil have been investigated, by applying impulses of increasing peak voltage until surface flashover occurred. The behavior of the materials in repeatedly over-volted gaps was also analyzed in terms of breakdown mode (some bulk sample breakdown behaviour was witnessed in this regime), time to breakdown, and breakdown voltage. Cylindrical samples of polypropylene, low-density polyethylene, ultra-high molecular weight polyethylene, and Rexolite, were held between two electrodes immersed in insulating oil, and subjected to average applied electrical fields up to 870 kV/cm. Tests were performed in both uniform- and non-uniform-fields, and with different sample topologies. In applied field measurements, polypropylene required the highest levels of average applied field to initiate flashover in all electrode configurations tested, settling at similar to 600 kV/cm in uniform fields, and similar to 325 kV/cm in non-uniform fields. In over-volted point-plane gaps, ultra-high molecular weight polyethylene exhibited the longest pre-breakdown delay times. The results will provide comparative data for system designers for the appropriate choice of dielectric materials to act as insulators for high-voltage, pulsed-power machines

Dynamic Voltage Scaling Aware Delay Fault Testing

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

Synthesis of all-digital delay lines

© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksThe synthesis of delay lines (DLs) is a core task during the generation of matched delays, ring oscillator clocks or delay monitors. The main figure of merit of a DL is the fidelity to track variability. Unfortunately, complex systems have a great diversity of timing paths that exhibit different sensitivities to static and dynamic variations. Designing DLs that capture this diversity is an ardous task. This paper proposes an algorithmic approach for the synthesis of DLs that can be integrated in a conventional design flow. The algorithm uses heuristics to perform a combinatorial search in a vast space of solutions that combine different types of gates and wire lengths. The synthesized DLs are (1) all digital, i.e., built of conventional standard cells, (2) accurate in tracking variability and (3) configurable at runtime. Experimental results with a commercial standard cell library confirm the quality of the DLs that only exhibit delay mismatches of about 1% on average over all PVT corners.Peer ReviewedPostprint (author's final draft

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

Non-enumerative Generation of Path Delay Distributions and its Application to Critical Path Selection

A Monte Carlo based approach is proposed capable of identifying in a non-enumerative and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths from a potentially exponential number of path candidates is presented. Paths and their delay distributions are stored in Zero Suppressed Binary Decision Diagrams. Experimental results on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed method is highly scalable and effective

Self-Organizing and Scalable Routing Protocol (SOSRP) for Underwater Acoustic Sensor Networks

Underwater Acoustic Sensor Networks (UASN) have two important limitations: a very aggressive (marine) environment, and the use of acoustic signals. This means that the techniques for terrestrial wireless sensor networks (WSN) are not applicable. This paper proposes a routing protocol called “Self-Organizing and Scalable Routing Protocol” (SOSRP) which is decentralized and based on tables residing in each node. A combination of the hop value to the collector node and the distance is used as a criterion to create routes leading to the sink node. The expected functions of the protocol include self-organization of the routes, tolerance to failures and detection of isolated nodes. Through the implementation of SOSRP in Matlab and a model of propagation and energy being appropriate for marine environment, performance results are obtained in different scenarios (varying both nodes and transmission range) that include parameters such as end-to-end packet delay, consumption of energy or length of the created routes (with and without failure). The results obtained show a stable, reliable and suitable operation for the deployment and operation of nodes in UASN networks

Adaptive Interest Rate Modelling

A good description of the dynamics of interest rates is crucial to price derivatives and to hedge corresponding risk. Interest rate modelling in an unstable macroeconomic context motivates one factor models with time varying parameters. In this paper, the local parameter approach is introduced to adaptively estimate interest rate models. This method can be generally used in time varying coefficient parametric models. It is used not only to detect the jumps and structural breaks, but also to choose the largest time homogeneous interval for each time point, such that in this interval, the coeffcients are statistically constant. We use this adaptive approach and apply it in simulations and real data. Using the three month treasure bill rate as a proxy of the short rate, we nd that our method can detect both structural changes and stable intervals for homogeneous modelling of the interest rate process. In more unstable macroeconomy periods, the time homogeneous interval can not last long. Furthermore, our approach performs well in long horizon forecasting.CIR model, Interest rate, Local parametric approach, Time homogeneous interval, Adaptive statistical techniques

User equilibrium traffic network assignment with stochastic travel times and late arrival penalty

The classical Wardrop user equilibrium (UE) assignment model assumes traveller choices are based on fixed, known travel times, yet these times are known to be rather variable between trips, both within and between days; typically, then, only mean travel times are represented. Classical stochastic user equilibrium (SUE) methods allow the mean travel times to be differentially perceived across the population, yet in a conventional application neither the UE or SUE approach recognises the travel times to be inherently variable. That is to say, there is no recognition that drivers risk arriving late at their destinations, and that this risk may vary across different paths of the network and according to the arrival time flexibility of the traveller. Recent work on incorporating risky elements into the choice process is seen either to neglect the link to the arrival constraints of the traveller, or to apply only to restricted problems with parallel alternatives and inflexible travel time distributions. In the paper, an alternative approach is described based on the ‘schedule delay’ paradigm, penalising late arrival under fixed departure times. The approach allows flexible travel time densities, which can be fitted to actual surveillance data, to be incorporated. A generalised formulation of UE is proposed, termed a Late Arrival Penalised UE (LAPUE). Conditions for the existence and uniqueness of LAPUE solutions are considered, as well as methods for their computation. Two specific travel time models are then considered, one based on multivariate Normal arc travel times, and an extended model to represent arc incidents, based on mixture distributions of multivariate Normals. Several illustrative examples are used to examine the sensitivity of LAPUE solutions to various input parameters, and in particular its comparison with UE predictions. Finally, paths for further research are discussed, including the extension of the model to include elements such as distributed arrival time constraints and penalties

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics