Dielectric Breakdown in Chemical Vapor Deposited Hexagonal Boron Nitride

Insulating films are essential in multiple electronic devices because they can provide essential functionalities, such as capacitance effects and electrical fields. Two-dimensional (2D) layered materials have superb electronic, physical, chemical, thermal, and optical properties, and they can be effectively used to provide additional performances, such as flexibility and transparency. 2D layered insulators are called to be essential in future electronic devices, but their reliability, degradation kinetics, and dielectric breakdown (BD) process are still not understood. In this work, the dielectric breakdown process of multilayer hexagonal boron nitride (h-BN) is analyzed on the nanoscale and on the device level, and the experimental results are studied via theoretical models. It is found that under electrical stress, local charge accumulation and charge trapping/detrapping are the onset mechanisms for dielectric BD formation. By means of conductive atomic force microscopy, the BD event was triggered at several locations on the surface of different dielectrics (SiO2, HfO2, Al2O3, multilayer h-BN, and monolayer h-BN); BD-induced hillocks rapidly appeared on the surface of all of them when the BD was reached, except in monolayer h-BN. The high thermal conductivity of h-BN combined with the one-atom-thick nature are genuine factors contributing to heat dissipation at the BD spot, which avoids self-accelerated and thermally driven catastrophic BD. These results point to monolayer h-BN as a sublime dielectric in terms of reliability, which may have important implications in future digital electronic devices.Fil: Jiang, Lanlan. Soochow University; ChinaFil: Shi, Yuanyuan. Soochow University; China. University of Stanford; Estados UnidosFil: Hui, Fei. Soochow University; China. Massachusetts Institute of Technology; Estados UnidosFil: Tang, Kechao. University of Stanford; Estados UnidosFil: Wu, Qian. Soochow University; ChinaFil: Pan, Chengbin. Soochow University; ChinaFil: Jing, Xu. Soochow University; China. University of Texas at Austin; Estados UnidosFil: Uppal, Hasan. University of Manchester; Reino UnidoFil: Palumbo, Félix Roberto Mario. Comisión Nacional de Energía Atómica; Argentina. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Lu, Guangyuan. Chinese Academy of Sciences; República de ChinaFil: Wu, Tianru. Chinese Academy of Sciences; República de ChinaFil: Wang, Haomin. Chinese Academy of Sciences; República de ChinaFil: Villena, Marco A.. Soochow University; ChinaFil: Xie, Xiaoming. Chinese Academy of Sciences; República de China. ShanghaiTech University; ChinaFil: McIntyre, Paul C.. University of Stanford; Estados UnidosFil: Lanza, Mario. Soochow University; Chin

Discrimination of surface and volume states in fully depleted field-effect devices on thick insulator substrates

The behavior of electronic devices fabricated on thin, lightly doped semiconductor layers can be significantly influenced by very low levels of non-ideal charge states. Such devices typically operate in a fully depleted mode, and can exhibit significantly different electrical properties and characteristics than their bulk material counterparts. Traditional interpretation of device characteristics may identify the existence of such non-idealities, but fail to ascertain if the origin is from within the semiconductor layer or associated with the interfaces to adjacent dielectric materials. This leads to ambiguity in how to rectify the behavior and improve device performance. Characterizing non-idealities through electrical means requires adaptations in both measurement techniques and data interpretation. Some of these adaptations have been applied in material systems like silicon-on-insulator (SOI), however in systems where the semiconductor film becomes increasingly isolated on very thick insulators (i.e., glass), the device physics of operation presents new challenges. Overcoming the obstacles in interpretation can directly aid the technology development of thin semiconductor films on thick insulator substrates. The investigation is initiated by isolating the interface of crystalline silicon bonded to a thick boro-aluminosilicate glass insulator. The interface is studied through traditional bulk capacitance-voltage (C-V) methods, and the electrical fragility of the interface is exposed. This reveals the necessity to discriminate between interface states and bulk defect states. To study methods of discrimination, the physics of field-effect devices fabricated on isolated semiconducting films is explained. These devices operate in a fully depleted state; expressions that describe the C-V relationship with a single gate electrode are derived and explored. The discussion presents an explanation of how surface and volume charge states each contribute to the C-V characteristic behavior. Application of this adapted C-V theory is then applied to the gated-diode, a novel device which has proven to be instrumental in charge state discrimination. Through this adaptation, the gated-diode is used to extract recombination-generation parameters isolated to the top surface, bottom surface and within the volume of the film. The methodology is developed through an exploration of devices fabricated on SOI and silicon-on-glass (SiOG) substrates, and furthers the understanding needed to improve material quality and device performance

Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures

Reliability Studies of TiN/Hf-Silicate Based Gate Stacks

Hafnium-silicate based oxides are among the leading candidates to be included into the first generation of high-Κ gate stacks in nano-scale CMOS technology because of their distinct advantages as far as thermal stability, leakage characteristics, threshold stability and low mobility degradation are concerned. Their reliability, which is limited by trapping at pre-existing and stress induced defects, remains to be a major concern. Energy levels of electrically active ionic defects within the thick high-Κ have been experimentally observed in the context of MOS band diagram for the first time in Hf-silicate gate stacks from low temperature and leakage measurements. Excellent match between experimental and calculated defect levels shows that bulk O vacancies are probably responsible for electron trapping at both shallow and deep levels. Their role in trapping and transport under different gate polarity and band bending conditions has been determined. For gate injection, electron transport through mid-gap states dominates, which leads to slow transient trapping at deep levels. Under substrate injection field and temperature dependent transport through conduction-edge shallow levels or trap-assisted tunneling due to negative- U transition occurs depending on bias condition. The former gives rise to fast transient trapping, whereas the latter is responsible for slow transient trapping. Mixed degradation, due to trapping of both electrons and holes in the trap levels within the bulk high-K, was observed under constant voltage stress (CVS) applied on n-channel MOS capacitors with negative bias condition. Mixed degradation resulted in turn-around effect in flat-band voltage shift (ΔFB) with respect to stress time. Under CVS with positive bias, applied on nMOSFETs, lateral distribution of trapped charges in the deep levels causes turn-around effect in threshold voltage shift (ΔVT) with respect to stress levels. For the incident carrier energies above the calculated 0 vacancy formation threshold and thick high-Κ layer, both flatband voltage shift, due to electron trapping at the deep levels, and increase in leakage current during stress follow tn(n ≈ 0.4) power-law dependence under substrate hot electron injection. Negative-U transitions to deep levels are shown to be responsible for the strong correlation between slow transient trapping and trap assisted tunneling. As far as negative bias temperature instability, NBTI effects on pMOSFETs is concerned, ΔVT is due to the mixed degradation within the bulk high-Κ for low bias conditions. For moderately high bias, ΔVT shows an excellent match with that of SiO, based devices, which is explained by reaction-diffusion (R-D) model of NBTL. Under high bias condition at elevated temperatures, due to high Si-H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation. Time-zero dielectric breakdown (TZBD) characteristics of TiN/HfO2 based gate stacks show that thickness and growth conditions significantly affect the BD field of IL. For the thin high-w layers, BD of IL triggers BD of the gate stack. Otherwise, BD of high-w layer initiates it. During time dependent dielectric breakdown, TDDB, four regimes of degradation are observed under CVS with high gate bias conditions: (i) charge trapping/defect generation, (ii) soft breakdown (SBD), (iii) progressive breakdown and (iv) hard breakdown (HBD). Activation energy of bond-breakage, found from Arrhenius plots of 63% failure value of TBD, shows that IL degradation triggers gate stacks BD, and the wear-out during TDDB

Reliability Analysis of Hafnium Oxide Dielectric Based Nanoelectronics

With the physical dimensions ever scaling down, the increasing level of sophistication in nano-electronics requires a comprehensive and multidisciplinary reliability investigation. A kind of nano-devices, HfO2-based high-k dielectric films, are studied in the statistical aspect of reliability as well as electrical and physical aspects of reliability characterization, including charge trapping and degradation mechanisms, breakdown modes and bathtub failure rate estimation. This research characterizes charge trapping and investigates degradation mechanisms in high-k dielectrics. Positive charges trapped in both bulk and interface contribute to the interface state generation and flat band voltage shift when electrons are injected from the gate under a negative gate bias condition.A negligible number of defects are generated until the stress voltage increases to a certain level. As results of hot electrons and positive charges trapped in the interface region, the difference in the breakdown sequence is attributed to the physical thickness of the bulk high-k layer and the structure of the interface layer. Time-to-breakdown data collected in the accelerated life tests are modeled with a bathtub failure rate curve by a 3-step Bayesian approach. Rather than individually considering each stress level in accelerating life tests (ALT), this approach derives the change point and the priors for Bayesian analysis from the time-to-failure data under neighborhood stresses, based on the relationship between the lifetime and stress voltage. This method can provide a fast and reliable estimation of failure rate for burn-in optimization when only a small sample of data is available

Resistance switching devices based on amorphous insulator-metal thin films

Nanometallic devices based on amorphous insulator-metal thin films are developed to provide a novel non-volatile resistance-switching random-access memory (RRAM). In these devices, data recording is controlled by a bipolar voltage, which tunes electron localization length, thus resistivity, through electron trapping/detrapping. The low-resistance state is a metallic state while the high-resistance state is an insulating state, as established by conductivity studies from 2K to 300K. The material is exemplified by a Si3N4 thin film with randomly dispersed Pt or Cr. It has been extended to other materials, spanning a large library of oxide and nitride insulator films, dispersed with transition and main-group metal atoms. Nanometallic RRAMs have superior properties that set them apart from other RRAMs. The critical switching voltage is independent of the film thickness/device area/temperature/switching speed. Trapped electrons are relaxed by electron-phonon interaction, adding stability which enables long-term memory retention. As electron-phonon interaction is mechanically altered, trapped electron can be destabilized, and sub-picosecond switching has been demonstrated using an electromagnetically generated stress pulse. AC impedance spectroscopy confirms the resistance state is spatially uniform, providing a capacitance that linearly scales with area and inversely scales with thickness. The spatial uniformity is also manifested in outstanding uniformity of switching properties. Device degradation, due to moisture, electrode oxidation and dielectrophoresis, is minimal when dense thin films are used or when a hermetic seal is provided. The potential for low power operation, multi-bit storage and complementary stacking have been demonstrated in various RRAM configurations.Comment: 523 pages, 215 figures, 10 chapter

Characterisation and modelling of degradation mechanisms in RF MEMS capacitive switches during hold-down operation

RF MEMS switches represent an attractive alternative technology to current mechanical (e.g. coaxial and waveguide) and solid-state (e.g. PIN diode and FET transistor) RF switch technologies. The materials and fabrication techniques used in MEMS manufacture enable mechanically moveable devices with high RF performance to be fabricated on a miniature scale. However, the operation of these devices is affected by several mechanical and electrical reliability concerns which limit device lifetimes and have so far prevented the widespread adoption and commercialisation of RF MEMS. While a significant amount of research and development on RF MEMS reliability has been performed in recent years, the degradation mechanisms responsible for these reliability concerns are still poorly understood. This is due to the multi-physical nature of MEMS switches where multiple mechanical and electrical degradation mechanisms can simultaneously affect device behaviour with no clear way of distinguishing between their individual effects. As such, little progress has been made in proposing solutions to these reliability concerns. While some RF MEMS switches have recently been commercialised, their success has come at the expense of decreased performance due to design changes necessarily imposed to prevent device failure. However, more high performance switches could be developed if the mechanisms responsible for reliability problems could be understood and solved. The work of this thesis is focussed on the isolation and study of individual reliability mechanisms in RF MEMS capacitive switches. A bipolar hold-down technique is used to minimise the effects of dielectric charging and allow mechanical degradation to be studied in isolation in aluminium-based capacitive switches. An investigation of mechanical degradation leads to the identification of grain boundary sliding as the physical process responsible for the decreased mechanical performance of a switch. An alternative material for the switch movable electrode is investigated and shown to be mechanically robust. The effects of dielectric charging are isolated from mechanical degradation using mechanically robust switches. The isolated investigation of dielectric charging leads to the identification of two major charging mechanisms which take place at the bulk and surface of the dielectric, respectively. The exchange of charge from interface traps is identified as the physical mechanism responsible for bulk dielectric charging. An investigation of surface dielectric charging reveals how this reliability concern depends on the structure and design of a switch. Finally, electrical and material means of minimising dielectric charging are investigated. The findings and results presented in this thesis represent a significant contribution to the state-of the- art understanding of RF MEMS capacitive switch reliability. By implementing the design changes and material solutions proposed in this work, the performance and lifetime of RF MEMS capacitive switches can be greatly improved

Embedded charge for microswitch applications

In this work a micro-electro-mechanical system (MEMS) is proposed for radio frequency (RF) switching applications. MEMS devices outperform the traditionally used solid-state devices in areas such as isolation, insertion loss, and linearity. However, micro switches suffer from high actuation voltage, lifetime limitations, and high packaging cost. A novel micro switch design that incorporates embedded charge in a cantilever structure can, in principle, enable low-voltage operation. This was the primary motivation for this stud