Design and implementation of a wideband sigma delta ADC

Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTƩ∆M), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications. The objective of this thesis is to design and implement a wideband CTƩ∆M for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTƩ∆M, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADC’s sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB. This thesis focuses on the design and implementation of the CTƩ∆M, building upon the principles of a discrete time Ʃ∆ modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTƩ∆ modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTƩ∆ modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTƩ∆M. The CTƩ∆Ms employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulator’s performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. Tiivistelmä. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistä tärkeämmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnän kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTƩ∆M), joissa käytetään ylinäytteistystä ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun. Tämän työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjärjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTƩ∆M, jolla on 15MHz:n signaalikaistanleveys. Ylinäytteistyssuhde on 25 ja AD muuntimen näytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR). Tämä työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Ʃ∆-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmä esitetään yksityiskohtaisesti, ja vaatimusten täyttyminen varmistetaan “top-down” -suunnitteluperiaatteella. Liitteenä on kertoimien laskemiseen käytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkän silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentä -DA muunninta. Viivekompensointipolkua käyttämällä modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. Lisäksi FIR takaisinkytkentä -DA-muuntimen käyttö pienentää kellojitteriherkkyyttä, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyä ja luotettavuutta. Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty peräkkäin integraattoreita myötäkytkentärakenteella (CIFF) ja toisessa sekä myötä- että takaisinkytkentärakenteella (CIFF-B). Päähuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa käyttäen 0.8 voltin käyttöjännitettä. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. Lisäksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin

Power Efficient Architectures for High Accuracy Analog-to-Digital Converters

Incremental ADCs (IADCs) have found wide applications in sensor interface circuitry since, compared to ∆Σ ADCs, they provide low-latency high-accuracy conversion and easy multiplexing among multiple channels. On the other hand, continuous-time ∆Σ ADCs (CTDSM) have been receiving more and more attention as a power-efficient solution in targeting medium to high accuracy over wider range of signal bandwidth (tens of MHz). In this dissertation, novel configurations have been explored in both architectures for power-efficient and high-accuracy data conversion. First, a multi-step incremental ADC (IADC) using multi-slope extended counting technique is described. Only one active integrator is used in the three-step conversion cycle. The accuracy of the IADC is extended by having it configured as multi-slope ADCs in two additional steps. The proposed IADC uses the same circuitry as a first-order IADC (IADC1), but it exhibits as good efficiency as its second-order ∆Σ ADC counterpart. For the same accuracy, the conversion cycle is shortened by a factor of more than 2⁹ compared to the IADC1. Fabricated in 0.18-μm CMOS process, the prototype ADC occupies 0.5 mm². With a 642 kHz clock, it achieves SNDR of 52.2 dB in the first step. The SNDR is boosted to 79.8 dB in the second step, and to 96.8 dB in the third step, over a 1 kHz signal band. The power consumption is 35 µW from a 1.5 V power supply. This gives an excellent Schreier FoM of 174.6 dB. Secondly, a multi-step incremental ADC with extended binary counting is proposed. It achieves high accuracy by splitting one conversion cycle into two serial steps. During the first step, the ADC works as a first-order incremental ADC (IADC1). The second step reuses the single integrator and extends the accuracy to 16 bits by a two-capacitor SAR-assisted binary counting technique. For the same accuracy, the conversion cycle is shortened by a factor of more than 2⁸ as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the SAR-assisted IADC achieves a peak SNR/SNDR/DR of 97.1/96.6/100.2 dB over a 1.2 kHz bandwidth, while dissipating 33.2 μW from a 1.5 V supply. This gives a Schreier FoM of 175.8 dB and Walden FoM of 0.25 pJ/conv.-step. Finally, the design of a continuous-time ∆Σ modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging is described. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 mm² and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit was achieved.Keywords: Incremental ADC, multi-step operation, instrumentation and measurement, sensor interface, analog-to-digital converter, extended counting, chopper stabilization, delta-sigma ADC, multi-slope ADCsKeywords: Incremental ADC, multi-step operation, instrumentation and measurement, sensor interface, analog-to-digital converter, extended counting, chopper stabilization, delta-sigma ADC, multi-slope ADC

Switched Capacitor Circuit Techniques for High Performance CMOS Analog Circuits

Switched capacitor (SC) circuits are the main building blocks in many structures such as filters, data converters, sampling circuits and sampled-data amplifiers. The key challenge is to design such circuits which are the prime components of any IoT system with low power consumption without compromising on the performance. In this dissertation, power efficient novel switched capacitor techniques have been explored to suppress noise and mitigate the slewing in switched capacitor-based analog to digital converters (ADCs). First, a two-step incremental ADC(IADC) with pseudo-pseudo differential (PPD) structure is presented. PPD integrators are implemented with added correlated level shifting (CLS) technique to relax the output swing and gain requirements of the operational transconductance amplifier (OTA). The two-step IADC is implemented with the first step configured as a single-bit first-order IADC and the second step, using a two-capacitor SAR-assisted extended counting to further enhances the accuracy. The design is demonstrated by implementing the prototype in 65nm CMOS technology. Second, new passive charge compensation techniques are described. The proposed techniques mitigate the slewing in the OTA by providing a controlled amount of charge to the output of the OTA. The effectiveness of the proposed charge compensation technique in a switched-capacitor integrator is demonstrated in a second-order DSM. Circuit-level simulations including the effects of process, voltage and temperature variations are also presented. The extracted simulation results show a 12 dB improvement in SNDR using the proposed technique compared to conventional DSM without charge compensation

Plasmonic color filter array, high performance analog to digital converter architectures and novel circuit techniques

Part I: Plasmonic color filters can be manufactured at lower cost since they can be fabricated in single lithographic process step as compared to Fabry-Perot based filters. In addition, they have narrow passband making resolving sharp features in sample spectrum possible. Due to these benefits, in this thesis, Plasmonic color filters are investigated as alternative to conventional color filters and their feasibility for spectroscopy demonstrated through reconstruction of 6 sample spectra by using a set of 20 color filters. The error in reconstructed sample spectra is less than 0.137 root mean squared error across all samples. Part II: A novel 12-bit pipelined successive approximation analog to digital converter is investigated for high speed data conversion. The design was implemented in TSMC 65nm process to demonstrate the feasibility of the architecture. Furthermore, a high dynamic range audio delta sigma modulator using pseudo-pseudo differential topology was investigated and feasibility simulated using TSMC 65nm process. In addition, various novel systems and circuit techniques including efficient calibration of feedback digital to analog converters, new boosted switch and push-pull source follower circuits were investigated to improve upon existing circuit topologies

An energy efficient noise-shaping SAR ADC in 28 nm FDSOI

In a noise-shaping SAR ADC, oversampling and noise shaping are used to increase the conversion accuracy beyond that the SAR exhibits alone. To implement the noise shaping, the residue voltage present at the SAR DAC plates after each conversion is exploited, and fed into a loop filter connected to an extra input of the SAR comparator. In this thesis, an energy efficient noise-shaping SAR ADC for medical ultrasound applications is designed in 28 nm FDSOI. The design specification is minimum 11.0 bit ENOB of accuracy, signal bandwidth of minimum 2 MHz, and sample rate of minimum 32MHz. According to post-layout Monte Carlo simulations, the designed ADC has an accuracy of 11.1 bit ENOB, and thus satisfies the accuracy requirement. The signal bandwidth and sample rate are the same as in the design specification. Specifically, the topics of this thesis are the design of the loop filter and its inter- facing towards the SAR, as well as the overall high level design. The 9-bit SAR used in the system is an already existing implementation. A cascaded FIR-IIR filter topology is used for the loop filter. In this work, the circuit implementation of this topology is improved, most importantly through the introduction of chopped buffers at the filter input. This eliminates signal attenuation due to charge sharing, and a DAC capacitance that is smaller than the sampling capacitance in the loop filter can therefore be used. Also, auto-zeroed, cascoded inverters rather than a standard OTA are used as gain elements in the switched-capacitor filter structure, and this leads to better energy efficiency. The designed ADC achieves a figure of merit (FOM) of 7.5fJ/conv-step in post-layout Monte Carlo simulations, and to the best of the author s knowledge, this is better than the current state-of-the-art of noise-shaping ADCs. When all kinds of ADCs are taken into consideration, the achieved FOM seems to be similar to the current state-of-the-art in the same specification range

Architectural Improvements Towards an Efficient 16-18 Bit 100-200 MSPS ADC

As Data conversion systems continue to improve in speed and resolution, increasing demands are placed on the performance of high-speed Analog to Digital Conversion systems. This work makes a survey about all these and proposes a suitable architecture in order to achieve the desired specifications of 100-200MS/s with 16-18 bit of resolution. The main architecture is based on paralleled structures in order to achieve high sampling rate and at the same time high resolution. In order to solve problems related to Time-interleaved architectures, an advanced randomization method was introduced. It combines randomization and spectral shaping of mismatches. With a simple low-pass filter the method can, compared to conventional randomization algorithms, improve the SFDR as well as the SINAD. The main advantage of this technique over previous ones is that, because the algorithm only need that ADCs are ordered basing on their time mismatches, the absolute accuracy of the mismatch identification method does not matter and, therefore, the requirements on the timing mismatch identification are very low. In addition to that, this correction system uses very simple algorithms able to correct not only for time but also for gain and offset mismatches

Improved design techniques for analog and mixed circuits

Although the digital revolution can realize many of past analog components in the digital forms, our world is surrounded with analog signals such as voice, temperature, etc. The bridge between these two worlds is one of key performance limitations among overall systems and it includes analog filters and data converters. This thesis studies two design techniques with respect to the improvement of the performances of the bridge circuits; one is an implementation of the delta-sigma A/D converter with a new architecture and another is a proposed correlated double-sampling technique for continuous analog filters. A circuit implementation for the new architecture converter is proposed and implemented in AKM 0.18µm CMOS technology. The test results show that the modulator achieves 72dB of SNDR from the 1.8 V supply voltage. A newly proposed correlated double sampling technique compensates the gain error of a high-Q Tow-Thomas filter which originates from the op-amp imperfections. The gain error is reduced to 0.6dB from 2.5dB with the correlated double sampling technique.Keywords: analog, continuous-time filter, mixed-mode, correlated double sampling, delta-sigma, dual-pat

Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected

High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion

The purpose of this thesis is the proposal and implementation of data conversion open-loop architectures based on voltage-controlled oscillators (VCOs) built with ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to the newest complementary metal-oxide-semiconductor (CMOS) nodes. The scaling of the design technologies into the nanometer range imposes the reduction of the supply voltage towards small and power-efficient architectures, leading to lower voltage overhead of the transistors. Additionally, phenomena like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between devices and PVT variations) make the design of classic structures for ADCs more challenging. In recent years, time-encoded A/D conversion has gained relevant popularity due to the possibility of being implemented with mostly digital structures. Within this trend, VCOs designed with ring oscillator based topologies have emerged as promising candidates for the conception of new digitization techniques. RO-based data converters show excellent scalability and sensitivity, apart from some other desirable properties, such as inherent quantization noise shaping and implicit anti-aliasing filtering. However, their nonlinearity and the limited time delay achievable in a simple NOT gate drastically limits the resolution of the converter, especially if we focus on wide-band A/D conversion. This thesis proposes new ways to alleviate these issues. Firstly, circuit-based techniques to compensate for the nonlinearity of the ring oscillator are proposed and compared to equivalent state-of-the-art solutions. The proposals are designed and simulated in a 65-nm CMOS node for open-loop RO-based ADC architectures. One of the techniques is also validated experimentally through a prototype. Secondly, new ways to artificially increase the effective oscillation frequency are introduced and validated by simulations. Finally, new approaches to shape the quantization noise and filter the output spectrum of a RO-based ADC are proposed theoretically. In particular, a quadrature RO-based band-pass ADC and a power-efficient Nyquist A/D converter are proposed and validated by simulations. All the techniques proposed in this work are especially devoted for highbandwidth applications, such as Internet-of-Things (IoT) nodes or maximally digital radio receivers. Nevertheless, their field of application is not restricted to them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas de conversión de datos basadas en osciladores en anillos, compatibles con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación más modernos donde las estructuras digitales se ven favorecidas. La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción de la tensión de alimentación para el desarrollo de arquitecturas pequeñas y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión para saturar transistores, lo que añadido a una ganancia cada vez menor de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones de proceso, tensión y temperatura han llevado a que sea cada vez más complejo el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión A/D basada en codificación temporal ha ganado gran popularidad dado que permite la implementación de estructuras mayoritariamente digitales. Como parte de esta evolución, los osciladores controlados por tensión diseñados con topologías de oscilador en anillo han surgido como un candidato prometedor para la concepción de nuevas técnicas de digitalización. Los convertidores de datos basados en osciladores en anillo son extremadamente sensibles (variación de frecuencia con respecto a la señal de entrada) así como escalables, además de otras propiedades muy atractivas, como el conformado espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta NOT restringen la resolución del conversor, especialmente para conversión A/D en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas técnicas para aliviar este tipo de problemas. En primer lugar, se proponen técnicas basadas en circuito para compensar el efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas presentadas es también validada experimentalmente a través de un prototipo. En segundo lugar, se introducen y validan por simulación varias formas de incrementar artificialmente la frecuencia de oscilación efectiva. Para finalizar, se proponen teóricamente dos enfoques para configurar nuevas formas de conformación del ruido de cuantificación y filtrado del espectro de salida de los datos digitales. En particular, son propuestos y validados por simulación un ADC pasobanda en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente para aplicaciones de alto ancho de banda, tales como módulos para el Internet de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar de ello, son extrapolables también a otros campos como el de la instrumentación biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí