Switched capacitor (SC) circuits are the main building blocks in many structures such as filters, data converters, sampling circuits and sampled-data amplifiers. The key challenge is to design such circuits which are the prime components of any IoT system with low power consumption without compromising on the performance. In this dissertation, power efficient novel switched capacitor techniques have been explored to suppress noise and mitigate the slewing in switched capacitor-based analog to digital converters (ADCs).
First, a two-step incremental ADC(IADC) with pseudo-pseudo differential (PPD) structure is presented. PPD integrators are implemented with added correlated level shifting (CLS) technique to relax the output swing and gain requirements of the operational transconductance amplifier (OTA). The two-step IADC is implemented with the first step configured as a single-bit first-order IADC and the second step, using a two-capacitor SAR-assisted extended counting to further enhances the accuracy. The design is demonstrated by implementing the prototype in 65nm CMOS technology.
Second, new passive charge compensation techniques are described. The proposed techniques mitigate the slewing in the OTA by providing a controlled amount of charge to the output of the OTA. The effectiveness of the proposed charge compensation technique in a switched-capacitor integrator is demonstrated in a second-order DSM. Circuit-level simulations including the effects of process, voltage and temperature variations are also presented. The extracted simulation results show a 12 dB improvement in SNDR using the proposed technique compared to conventional DSM without charge compensation
