A real-time defect detection in printed circuit boards applying deep learning

Inspection of defects in the printed circuit boards (PCBs) has both safety and economic significance in the 4.0 industrial manufacturing. Nevertheless, it is still a challenging problem to be studied in-depth due to the complexity of the PCB layouts and the shrinking down tendency of the electronic component size. In this paper, a real-time automated supervision algorithm is proposed to test the PCBs quality among different scenarios. The density of the PCBs layout and the complexity on the surface are analyzed based on deep learning and image feature extraction algorithms. To be more detailed, the ORB feature and the Brute-force matching method are utilized to match perfectly the input images with the PCB templates. After transferring images by aiding the RANSAC algorithm, a hybrid method using modern computer vision algorithms is developed to segment defective areas on the PCBs surface. Then, by applying the enhanced Residual Network –50, the proposed algorithm can classify the groove defects on the surface mount technology electronic components which minimum size up to 1x3 mm. After the training process, the proposed system is capable to categorize various types of overproduced, recycled, and cloned PCBs. The speed of the quality testing operation maintains at a high level with an average precision rate up to 96.29 % in case of good brightness conditions. Finally, the computational experiments demonstrate that the proposed system based on deep learning can obtain superior results and it outperforms several existing works in terms of speed, precision, and robustnes

Phase Locking Authentication for Scan Architecture

Scan design is a widely used Design for Testability (DfT) approach for digital circuits. It provides a high level of controllability and observability resulting in a high fault coverage. To achieve a high level of testability, scan architecture must provide access to the internal nodes of the circuit-under-test (CUT). This access however leads to vulnerability in the security of the CUT. If an unrestricted access is provided through a scan architecture, unlimited test vectors can be applied to the CUT and its responses can be captured. Such an unrestricted access to the CUT can potentially undermine the security of the critical information stored in the CUT. There is a need to secure scan architecture to prevent hardware attacks however a secure solution may limit the CUT testability. There is a trade-off between security and testability, therefore, a secure scan architecture without hindering its controllability and observability is required. Three solutions to secure scan architecture have been proposed in this thesis. In the first method, the tester is authenticated and the number of authentication attempts has been limited. In the second method, a Phase Locked Loop (PLL) is utilized to secure scan architecture. In the third method, the scan architecture is secured through a clock and data recovery (CDR) technique. This is a manuscript based thesis and the results of this study have been published in two conference proceedings. The latest results have also been prepared as an article for submission to a high rank conference

The inspection quality to detect scratch using robot vision

Automated Robotic vision helps to prevent quality problems from occurring.In this research, the concept and operation of robot inspection in fabricating the integrated circuit (IC) is being discussed comprehensively.The results showed the advantages and disadvantages of using this technology to further improve the quality of IC fabricatio

Design for pre-bond testability in 3D integrated circuits

In this dissertation we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is wrapped in test control logic that both manages tier test pre-bond and integrates the tier into the large test architecture post-bond. We describe a new kind of boundary scan to provide the necessary test control and observation of the partial circuits, and we propose a new design methodology for test hardcore that ensures both pre-bond functionality and post-bond optimality. We present the application of these techniques to the 3D-MAPS test vehicle, which has proven their effectiveness. Second, we extend these DFT techniques to circuit-partitioned designs. We find that boundary scan design is generally sufficient, but that some 3D designs require special DFT treatment. Most importantly, we demonstrate that the functional partitioning inherent in 3D design can potentially decrease the total test cost of verifying a circuit. Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm co-designs the pre-bond and post-bond wrappers to simultaneously minimize test time and routing cost. On average, our algorithm utilizes over 90% of the wires in both the pre-bond and post-bond wrappers. Finally, we look at the 3D vias themselves to develop a low-cost, high-volume pre-bond test methodology appropriate for production-level test. We describe the shorting probes methodology, wherein large test probes are used to contact multiple small 3D vias. This technique is an all-digital test method that integrates seamlessly into existing test flows. Our experimental results demonstrate two key facts: neither the large capacitance of the probe tips nor the process variation in the 3D vias and the probe tips significantly hinders the testability of the circuits. Taken together, this body of work defines a complete test methodology for testing 3D ICs pre-bond, eliminating one of the key hurdles to the commercialization of 3D technology.PhDCommittee Chair: Lee, Hsien-Hsin; Committee Member: Bakir, Muhannad; Committee Member: Lim, Sung Kyu; Committee Member: Vuduc, Richard; Committee Member: Yalamanchili, Sudhaka

Reliability of CGA/LGA/HDI Package Board/Assembly (Final Report)

Package manufacturers are now offering commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronics packages. The previous reports, released in January of 2012 and January of 2013, presented package test data, assembly information, and reliability evaluation by thermal cycling for CGA packages with 1752, 1517, 1509, and 1272 inputs/outputs (I/Os) and 1-mm pitch. It presented the thermal cycling (-55C either 100C or 125C) test results for up to 200 cycles. This report presents up to 500 thermal cycles with quality assurance and failure analysis evaluation represented by optical photomicrographs, 2D real time X-ray images, dye-and-pry photomicrographs, and optical/scanning electron Microscopy (SEM) cross-sectional images. The report also presents assembly challenge using reflowing by either vapor phase or rework station of CGA and land grid array (LGA) versions of three high I/O packages both ceramic and plastic configuration. A new test vehicle was designed having high density interconnect (HDI) printed circuit board (PCB) with microvia-in-pad to accommodate both LGA packages as well as a large number of fine pitch ball grid arrays (BGAs). The LGAs either were assembled onto HDI PCB as an LGA or were solder paste print and reflow first to form solder dome on pads before assembly. Both plastic BGAs with 1156 I/O and ceramic LGAs were assembled. It also presented the X-ray inspection results as well as failures due to 200 thermal cycles. Lessons learned on assembly of ceramic LGAs are also presented

Through-Life Monitoring of the impact of vibration on the reliability of area array packages using Non- Destructive Testing

In order to keep up with the demands for faster, cheaper and smaller electronics, the packaging industry has evolved tremendously. Area array packages like flip chips and ball grid arrays are therefore widely used in modern day electronics. However, from the reliability standpoint, solder joints in these area array packages are often the weakest link. In case of harsh vibration environments like military and automobile applications, joint failure mainly occurs due to the high stress incurred during extreme environmental conditions that lead to fatigue failures. This thesis aims to study the effects of real time vibration on area array packages (flip chips in particular) using acoustic micro imaging for through life monitoring of the solder joints. Since real time vibration on solder joints have not been studied before, the various steps for successful testing, through life monitoring of the solder joints and data analysis will be investigated and discussed. Based on automobile industry standards, a real time vibration profile was obtained with the help of Delphi experts, who are the industry collaborators of this project. Due to its strong capability to detect discontinuities within materials and interconnections, Acoustic Micro Imaging (AMI) also known as Scanning Acoustic Microscopy (CSAM) has been used to monitor the solder joints. This approach has not previously been used as an effective tool in monitoring solder joints through life performance in vibration testing. The research regime proposed in this thesis was to monitor the health of solder joints through ultrasound images from beginning to failure, and to see how cracks initiate and propagate in them. The effect of the relative position and orientation on the reliability of the solder joints and the flip chips in the PCB was also studied. The data collected was analysed using MATLAB. The results have shown that three types of solder joints- healthy, partially fractured or fractured are formed near the time of complete failure of a flip chip. When about 70- 80% of the flip chips are either partially fractured or fractured a flip chip is expected to fail. The mean pixel intensity and area change in the acoustic image of a partially fractured or fully fractured joint tends to be higher compared to a healthy joint. Crack initiation in a joint occurs at around 35-40% cycling and propagates linearly till 80-85% cycling after which a joint fails. A statistical analysis done on the solder joints showed that the intensity distribution of healthy joints follow a simple Gaussian distribution while that of partially fractured or fractured joint can only be represented by using a mixture of Gaussians. The solder joints near the board edges are the least reliable in a vibration environment. However, solder joints with back to back connections are more reliable than the ones placed in one sided orientation. The most reliable flip chip orientation in a vibration environment is the back to back connection with no offset which was actually found to be the least reliable in the case of thermal cycling. Based on the analysis of the results, a few design guidelines for flip chip layout and orientations in a PCB has also been proposed in this work

PCB Quality Metrics that Drive Reliability (PD 18)

Risk based technology infusion is a deliberate and systematic process which defines the analysis and communication methodology by which new technology is applied and integrated into existing and new designs, identifies technology development needs based on trends analysis and facilitates the identification of shortfalls against performance objectives. This presentation at IPC Works Asia Aerospace 2019 Events provides the audience a snapshot of quality variations in printed wiring board quality, as assessed, using experiences in processing and risk analysis of PWB structural integrity coupons. The presentation will focus on printed wiring board quality metrics used, the relative type and number of non-conformances observed and trend analysis using statistical methods. Trend analysis shows the top five non-conformances observed across PWB suppliers, the root cause(s) behind these non-conformance and suggestions of mitigation plans. The trends will then be matched with the current state of the PWB supplier base and its challenges and opportunities. The presentation further discusses the risk based SMA approaches and methods being applied at GSFC for evaluating candidate printed wiring board technologies which promote the adoption of higher throughput and faster processing technology for GSFC missions

Methodology and Ecosystem for the Design of a Complex Network ASIC

Performance of HPC systems has risen steadily. While the 10 Petaflop/s barrier has been breached in the year 2011 the next large step into the exascale era is expected sometime between the years 2018 and 2020. The EXTOLL project will be an integral part in this venture. Originally designed as a research project on FPGA basis it will make the transition to an ASIC to improve its already excelling performance even further. This transition poses many challenges that will be presented in this thesis. Nowadays, it is not enough to look only at single components in a system. EXTOLL is part of complex ecosystem which must be optimized overall since everything is tightly interwoven and disregarding some aspects can cause the whole system either to work with limited performance or even to fail. This thesis examines four different aspects in the design hierarchy and proposes efficient solutions or improvements for each of them. At first it takes a look at the design implementation and the differences between FPGA and ASIC design. It introduces a methodology to equip all on-chip memory with ECC logic automatically without the user’s input and in a transparent way so that the underlying code that uses the memory does not have to be changed. In the next step the floorplanning process is analyzed and an iterative solution is worked out based on physical and logical constraints of the EXTOLL design. Besides, a work flow for collaborative design is presented that allows multiple users to work on the design concurrently. The third part concentrates on the high-speed signal path from the chip to the connector and how it is affected by technological limitations. All constraints are analyzed and a package layout for the EXTOLL chip is proposed that is seen as the optimal solution. The last part develops a cost model for wafer and package level test and raises technological concerns that will affect the testing methodology. In order to run testing internally it proposes the development of a stand-alone test platform that is able to test packaged EXTOLL chips in every aspect