Impact of the substrate and buffer design on the performance of GaN on Si power HEMTs

Abstract This paper presents an extensive analysis of the impact of substrate and buffer properties on the performance and breakdown voltage of E-mode power HEMTs. We investigated the impact of buffer thickness, substrate resistivity and substrate miscut angle, by characterizing several wafers by means of DC and pulsed measurement. The results demonstrate that: (i) the resistivity of the silicon substrate strongly impacts on the breakdown voltage and vertical leakage current. In fact, highly resistive substrates may partly deplete under high vertical bias, thus limiting the total potential drop on the epitaxial layers. As a consequence, the vertical I V plots show a "plateau", that limits the vertical leakage. (ii) the depletion of the substrate may worsen the dynamic performance of the devices, due to an enhancement of buffer trapping. (iii) Larger buffer thickness results in an increased robustness of the vertical stack, due to the thicker insulating region. (iv) the miscut angle (0°, 0.5°, and 1°) can significantly impact on both threshold voltage and the 2DEG density; devices with miscut substrate have higher current density. On the other hand, the dynamic on-resistance variation is comparable in the three cases

GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs

GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ( \u3c 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition

Design, Fabrication and Characterization of GaN HEMTs for Power Switching Applications

The unique properties of the III-nitride heterostructure, consisting of gallium nitride (GaN), aluminium nitride (AlN) and their ternary compounds (e.g. AlGaN, InAlN), allow for the fabrication of high electron mobility transistors (HEMTs). These devices exhibit high breakdown fields, high electron mobilities and small parasitic capacitances, making them suitable for wireless communication and power electronic applications. In this work, GaN-based power switching HEMTs and low voltage, short-channel HEMTs were designed, fabricated, and characterized.In the first part of the thesis, AlGaN/GaN-on-SiC high voltage metal-insulator-semiconductor (MIS)HEMTs fabricated on a novel ‘buffer-free’ heterostructure are presented. This heterostructure effectively suppresses buffer-related trapping effects while maintaining high electron confinement and low leakage currents, making it a viable material for high voltage, power electronic HEMTs. This part of the thesis covers device processing techniques to minimize leakage currents and maximize breakdown voltages in these ‘buffer-free’ MISHEMTs. Additionally, a recess-etched, Ta-based, ohmic contact process was utilized to form low-resistive ohmic contacts with contact resistances of 0.44-0.47 Ω∙mm. High voltage operation can be achieved by employing a temperature-stable nitrogen implantation isolation process, which results in three-terminal breakdown fields of 98-123 V/μm. By contrast, mesa isolation techniques exhibit breakdown fields below 85 V/μm and higher off-state leakage currents. Stoichiometric low-pressure chemical vapor deposition (LPCVD) SiNx passivation layers suppress gate currents through the AlGaN barrier below 10 nA/mm over 1000 V, which is more than two orders of magnitude lower compared to Si-rich SiNx passivation layers. A 10% dynamic on-resistance increase at 240 V was measured in HEMTs with stoichiometric SiNx passivation, which is likely caused by slow traps with time constants over 100 ms. SiNx gate dielectrics display better electrical isolation at high voltages compared to HfO2 and Ta2O5. However, the two gate oxides exhibit threshold voltages (Vth) above -2 V, making them a promising alternative for the fabrication of recess-etched normally-off MISHEMTs.Reducing the gate length (Lg) to minimize losses and increase the operating frequency in GaN HEMTs also entails more severe short-channel effects (SCEs), limiting gain, output power and the maximum off-state voltage. In the second part of the thesis, SCEs were studied in short-channel GaN HEMTs using a drain-current injection technique (DCIT). The proposed method allows Vth to be obtained for a wide range of drain-source voltages (Vds) in one measurement, which then can be used to calculate the drain-induced barrier lowering (DIBL) as a rate-of-change of Vth with respect to Vds. The method was validated using HEMTs with a Fe-doped GaN buffer layer and a C-doped AlGaN back-barrier with thin channel layers. Supporting technology computer-aided design (TCAD) simulations indicate that the large increase in DIBL is caused by buffer leakage. This method could be utilized to optimize buffer design and gate lengths to minimize on-state losses and buffer leakage currents in power switching HEMTs

Optimization of Ohmic Contacts and Surface Passivation for ‘Buffer-Free’ GaN HEMT Technologies

Gallium nitride high electron mobility transistors (GaN HEMTs) draw attention from high frequency and high power industries due to unique properties including high electron mobility and saturation velocity combined with high breakdown voltage. This makes GaN HEMTs suitable for power devices with high switching speed and high frequency applications with high power density requirements. However, the device performance is still partly limited by problems associated with the formation of low resistivity ohmic contact, trapping effects, and the confinement of the two-dimensional electron gas (2DEG).\ua0\ua0\ua0 In this work, reproducible deeply recessed Ta-based ohmic contacts with a low contact resistance of 0.2 - 0.3 Ωmm, a low annealing temperature of 550 - 600 \ub0C, and a large process window were optimized. Low annealing temperature reduces the risk of 2DEG degradation and promotes better morphology of the ohmic contacts. Deeply recessed ohmic contacts beyond the barrier layers make the process less sensitive to the etching depth since the ohmic contacts are formed on the sidewall of the recess. The concept of deeply recessed low resistivity ohmic contacts is also successfully demonstrated on different epi-structures with different barrier designs.\ua0\ua0\ua0 Passivation with silicon nitride (SiN) is an effective method to suppress electron trapping effects. Low Pressure Chemical Vapor Deposition (LPCVD) of SiN has shown to result in high quality dielectrics with excellent passivation effect. However, the surface traps are not fully removed after passivation due to dangling-bonds and native oxide layer at the interface of passivation and epi-structure. Therefore, a plasma-free in-situ NH3 pretreatment method before the deposition of the SiN passivation was studied. The samples with the pretreatment present a 38% lower surface-related current collapse and a 50% lower dynamic on-resistance than the samples without the pretreatment. The improved dynamic performance and lower dispersion directly yield a 30% higher output power of (3.4 vs. 2.6 W/mm) and a better power added efficiency (44% vs. 39%) at 3 GHz. Furthermore, it was found that a longer pretreatment duration improves the uniformity of device performance.\ua0\ua0\ua0 Traditionally, decreasing leakage currents in the buffer and improving electron confinement to the 2DEG are achieved by intentional acceptor-like dopants (iron and carbon) in the GaN buffer and back-barrier layer made by a ternary III-nitride material. However, electron trapping effects and thermal resistivity increase due to the dopants and the ternary material, respectively. In this thesis, a novel approach, where a unique epitaxial scheme permits a thickness reduction of the unintentional-doped (UID) GaN layer down to 250 nm, as compared to a normal thickness of 2 μm. In this way, the AlN nucleation layer effectively act as a back-barrier. The approached, named QuanFINE is investigated and benchmarked to a conventional epi-structure with a thick Fe-doped-GaN buffer. A 2DEG mobility of 2000 cm^2/V-s and the 2DEG concentration of 1.1∙10^13 cm^-2 on QuanFINE indicate that the 2DEG properties are not sacrificed with a thin UID-GaN layer. Thanks to the thin UID-GaN layer of QuanFINE, trapping effects are reduced. Comparable output power of 4.1 W/mm and a PAE of 40% at 3 GHz of both QuanFINE and conventional Fe-doped thick GaN buffer sample are measured

The 2018 GaN Power Electronics Roadmap

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here