MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap

The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies

Semiconductor Packaging

In semiconductor manufacturing, understanding how various materials behave and interact is critical to making a reliable and robust semiconductor package. Semiconductor Packaging: Materials Interaction and Reliability provides a fundamental understanding of the underlying physical properties of the materials used in a semiconductor package. By tying together the disparate elements essential to a semiconductor package, the authors show how all the parts fit and work together to provide durable protection for the integrated circuit chip within as well as a means for the chip to communicate with the outside world. The text also covers packaging materials for MEMS, solar technology, and LEDs and explores future trends in semiconductor packages

The Development of Novel Interconnection Technologies for 3D Packaging of Wire Bondless Silicon Carbide Power Modules

This dissertation advances the cause for the 3D packaging and integration of silicon carbide power modules. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were investigated, and the concept for a novel SiC power module was discussed. This highly-integrated SiC power module was assessed for feasibility, with a focus on achieving ultralow parasitic inductances in the critical switching loops. This will enable higher switching frequencies, leading to a reduction in the size of the passive devices in the system and resulting in systems with lower weight and volume. The proposed concept yielded an order-of-magnitude reduction in system parasitics, alongside the possibility of a compact system integration. The technological barriers to realizing these concepts were identified, and solutions for novel interconnection schemes were proposed and evaluated. A novel sintered silver preform was developed to facilitate flip-chip interconnections for a bare-die power device while operating in a high ambient temperature. The preform was demonstrated to have 3.75× more bonding strength than a conventional sintered silver bond and passed rigorous thermal shock tests. A chip-scale and flip-chip capable power device was also developed. The novel package combined the ease of assembly of a discrete device with a performance exceeding a wire bonded module. It occupied a 14× smaller footprint than a discrete device, and offered power loop inductances which were less than a third of a conventional wire bonded module. A detailed manufacturing process flow and qualification is included in this dissertation. These novel devices were implemented in various electrical systems—a discrete Schottky barrier diode package, a half-bridge module with external gate drive, and finally a half-bridge with integrated gate driver in-module. The results of these investigations have been reported and their benefits assessed. The wire bondless modules showed \u3c 5% overshoot under all test conditions. No observable detrimental effects due to dv/dt were observed for any of the modules even under aggressive voltage slew rates of 20-25 V/ns

Semiconductor Packaging

In semiconductor manufacturing, understanding how various materials behave and interact is critical to making a reliable and robust semiconductor package. Semiconductor Packaging: Materials Interaction and Reliability provides a fundamental understanding of the underlying physical properties of the materials used in a semiconductor package. By tying together the disparate elements essential to a semiconductor package, the authors show how all the parts fit and work together to provide durable protection for the integrated circuit chip within as well as a means for the chip to communicate with the outside world. The text also covers packaging materials for MEMS, solar technology, and LEDs and explores future trends in semiconductor packages

Trends in assembling of advanced IC packages, Journal of Telecommunications and Information Technology, 2005, nr 1

In the paper, an overview of the current trends in the development of advanced IC packages will be presented. It will be shown how switching from peripheral packages (DIP, QFP) to array packages (BGA, CSP) and multichip packages (SiP, MCM) affects the assembly processes of IC and performance of electronic systems. The progress in bonding technologies for semiconductor packages will be presented too. The idea of wire bonding, flip chip and TAB assembly will be shown together with the boundaries imposed by materials and technology. The construction of SiP packages will be explained in more detail. The paper addresses also the latest solutions in MCM packages

High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

Non-destructive evaluation of solder joint reliability

A through life non-destructive evaluation technique is presented in which a key solder joint feature, nucleating at the bump to silicon interface and propagating across a laminar crack plane is captured and tracked using acoustic microscopy imaging (AMI). The feasibility of this concept was successfully demonstrated by employing the measurement technique in combination with Finite Element Analysis (FEA) to study the impact of component floor plan layout on the reliability of electronics systems subjected to thermal cycling. A comprehensive review of current and emerging packaging and interconnect technologies has shown increasingly a move from conventional 2D to 3D packaging. These present new challenges for reliability and Non Destructive Evaluation (NDE) due to solder joints being hidden beneath the packaging, and not ordinarily visible or accessible for inspection. Solutions are developed using non-destructive testing (NDT) techniques that have the potential to detect and locate defects in microelectronic devices. This thesis reports on X-ray and Acoustic Micro Imaging (AMI) which have complementary image discriminating features. Gap type defects are hard to find using X-ray alone due to low contrast and spot size resolution, whereas AMI having better axial resolution has allowed cracks and delamination at closely spaced interfaces to be investigated. The application of AMI to the study of through life solder joint behaviour has been achieved for the first time. Finite Element Analysis and AMI performance were compared to measure solder joint reliability for several realistic test cases. AMI images were taken at regular intervals to monitor through- life behaviour. Image processing techniques were used to extract a diameter measurement for a laminar crack plane, within a solder joint damage region occurring at the bump to silicon interface. FEA solder joint reliability simulations for flip-chip and micro-BGA (mBGA) packages placed on FR4 PCB's were compared to the AMI measurement performance, with a reasonable level of correlation observed. Both techniques clearly showed significant reliability degradation of the critical solder joints located furthest from the neutral axis of the package, typically residing at the package corners. The technique also confirmed that circuit board thickness can affect interconnect reliability, as can floor plan. Improved correlation to the real world environment was achieved when simulation models considered the entire floor plan layout and constraints imposed on the circuit board assembly. This thesis established a novel through life solder joint evaluation method crucial to the development of better physics of failure models and the advancement of model based prognostics in electronics systems

Reliability evaluation of stacked die BGA assemblies under mechanical bending loads

This thesis presents a reliability evaluation of stacked die ball grid array (BGA) assemblies under mechanical bending loads. The test specimens used in this investigation were four die stacked BGAs assembled on printed circuit boards (PCBs) with eutectic tin-lead solder and gold over nickel finishes, both as-reflowed and after aging. The failure envelopes of both types of specimen were quantified in terms of PCB flexural strain and strain rate. The experimental data from cyclic bending tests at three strain amplitudes with a constant strain rate have been used to determine the effect of strain amplitudes on cycles to failure. The experimental data from cyclic bending tests were combined with the data from impact tests to determine the effect of strain rate to cycles to failure. The failure sites associated with each test condition were identified, and failure site transition phenomena are reported and discussed

Développement de procédés avancés d'encapsulation de composants microélectroniques basés sur les techniques de thermocompression

L'un des grands défis de la recherche et développement est d'optimiser l'ensemble du cycle de fabrication d'un produit microélectronique, depuis sa conception jusqu’à sa tenue mécanique en service. Un objectif essentiel des entreprises était de réduire le temps de cycles d’assemblage afin de minimiser les coûts de production. La phase d’assemblage des composants microélectroniques est l'une des étapes clé qui doit être bien optimisée afin d’atteindre l’objectif de minimisation du temps de cycle. La méthode d'assemblage traditionnelle des puces par refusion (en anglais mass reflow MR) convenait généralement à une fabrication à grand volume, en particulier pour des puces à pas standard d'environ 150 μm. Cependant, la forte demande du marché pour des interconnexions à pas plus fin, pour permettre un nombre d'entrée/sortie (Input/Output : I/O) plus élevé dans un facteur de forme plus petit, a entraîné une transition du processus de la liaison MR conventionnel à l'assemblage par thermocompression (en anglais ThermoCompression Bonding TCB). Bien que le procédé TCB offre un assemblage de plus grande précision et permet l'utilisation des pas d'interconnexion plus fins, il présente également de nouveaux défis. L'un des problèmes majeurs de l'assemblage TCB est qu'il s'agit d'un processus assez long, dans lequel chaque puce doit être passée indépendamment à travers un cycle TCB complet, incluant le chauffage, le maintien de la température et le refroidissement. Cela entraîne une diminution significative de la productivité par rapport au MR. Le débit de production peut être amélioré en réduisant le temps nécessaire pour atteindre les températures de processus requises. Cependant, des variations thermiques peuvent se produire aux interfaces de liaison, entraînant une mauvaise uniformité de température sur la surface de la puce et conduisant à des régions où le point de fusion de la brasure n'est pas atteint. Ainsi, il est extrêmement important de prévoir et contrôler la température réelle à l'interface de liaison afin d’obtenir une bonne uniformité thermique et des joints de brasure sans défaut. C'est dans cette perspective que s'inscrit les travaux menés dans la première partie de la thèse. Le premier objectif de cette étude était donc de déterminer la durée minimum de temps de chauffe nécessaire assurant une uniformité de température optimal et par conséquent des joints de brasure de bonne qualité. Pour atteindre cet objectif, il fallait alors proposer et valider une nouvelle méthodologie pour estimer la température d'interface lors d'un processus TCB. Une évaluation de l'influence de différentes vitesses de chauffe sur la distribution de température à travers la surface de la puce, ainsi que sur la qualité de liaison résultante, a été réalisée à l’aide d’un capteur de type RTD (). Les résultats ont montré que les défauts de brasure observés aux interfaces de liaison peuvent éventuellement être liés à une mauvaise uniformité de température, liée à des vitesses de chauffe élevées. Des variations thermiques acceptables ont été trouvées à une faible vitesse de chauffage de 80°C/s. Par conséquent, pour surmonter les températures de processus élevées et leurs effets néfastes sur la productivité, le développement d'une nouvelle méthode d’assemblage TCB à basse température devient primordiale. Le développement d’une nouvelle méthode de liaison par thermocompression à l'état solide détecteur de température résistif, Resistance Temperature Detector en anglais était donc notre second objectif dans cette étude. Cette méthode est basée sur la création d'une liaison mécanique temporaire initiale au début du processus de packaging (en utilisant une pression à une température inférieure au point de fusion de la brasure). Les joints de iv brasure seront entièrement refondus à la fin du processus de packaging, lorsque les billes de brasure BGA (ball-grid-array) seront brasées au substrat. Cette nouvelle méthode peut surmonter les limitations associées au processus TCB conventionnel, notamment la température élevée, le processus d'assemblage lent et les contraintes mécaniques élevées. Une investigation a été menée pour déterminer les conditions d'assemblage appropriées à appliquer pendant ce processus. Des investigations supplémentaires ont été également menées pour explorer le mécanisme d'assemblage responsable de l’assemblage mécanique temporaire. Les résultats préliminaires de cette méthode sont prometteurs, montrant des joints de brasure de bonne qualité formés en un temps d'assemblage très court (6 secondes) et à des températures bien inférieures au TCB conventionnel (200°C)