Test-Cost Modeling and Optimal Test-Flow Selection of 3D-Stacked ICs

Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost.We propose a generic cost model to account for various test costs involved in 3D integration and present a formal representation of the solution space to minimize the overall cost. We present an algorithm based on A*—a best-first search technique—to obtain an optimal solution. An approximation algorithm with provable bounds on optimality is proposed to further reduce the search space. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed method. Adopting a formal approach to solving the cost-minimization problem provides useful insights that cannot be derived via selective enumeration of a smaller number of candidate test flows.This research was supported in part by the National Science Foundation under grant no. CCF-1017391, the Semiconductor Research Corporation under contract no. 2118, a grant from Intel Corporation, and a gift from Cisco Systems through the Silicon Valley Community Foundation

A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators

International audience3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues, especially for TSVs. In this paper we propose a novel Built-In-Self-Test (BIST) architecture for pre-bond testing of TSVs in 3D stacked integrated circuits. The main idea is to measure the variation of TSVs capacitances in order to detect defective TSVs. The BIST architecture is based on ring oscillators, frequencies of which depend on TSVs capacitances. The proposed BIST is integrated within the JTAG standard. This paper presents spice simulation results and logic synthesis results of the proposed TSV ring oscillator structure using a 65 nm CMOS technology, including 10 μm diameter TSV middle technology. Due to local process variations, the proposed test architecture is limited in accuracy; it detects only large capacitive faults on TSVs

Thermo-Mechanical Effects Of Thermal Cycled Copper Through Silicon Vias

The semiconductor industry is currently facing transistor scaling issues due to fabrication thresholds and quantum effects. In this \u27More-Than-Moore\u27 era, the industry is developing new ways to increase device performance, such as stacking chips for three-dimensional integrated circuits (3D-IC). The 3D-IC\u27s superior performance over their 2D counterparts can be attributed to the use of vertical interconnects, or through silicon vias (TSV). These interconnects are much shorter, reducing signal delay. However TSVs are susceptible to various thermo-mechanical reliability concerns. Heating during fabrication and use, in conjunction with coefficient of thermal expansion mismatch between the copper TSVs and silicon substrate, create harmful stresses in the system. The purpose of this work is to evaluate the signal integrity of Cu-TSVs and determine the major contributing factors of the signal degradation upon in-use conditions. Two series of samples containing blind Cu-TSVs embedded in a Si substrate were studied, each having different types and amounts of voids from manufacturing. The samples were thermally cycled up to 2000 times using three maximum temperatures to simulate three unique in-use conditions. S11 parameter measurements were then conducted to determine the signal integrity of the TSVs. To investigate the internal response from cycling, a protocol was developed for cross-sectioning the copper TSVs. Voids were measured using scanning electron microscope and focused ion beam imaging of the cross-sections, while the microstructural evolution of the copper was monitored with electron backscattering diffraction. An increase in void area was found to occur after cycling. This is thought to be the major contributing factor in the signal degradation of the TSVs, since no microstructural changes were observed in the copper

A Comprehensive Study of the Hardware Trojan and Side-Channel Attacks in Three-Dimensional (3D) Integrated Circuits (ICs)

Three-dimensional (3D) integration is emerging as promising techniques for high-performance and low-power integrated circuit (IC, a.k.a. chip) design. As 3D chips require more manufacturing phases than conventional planar ICs, more fabrication foundries are involved in the supply chain of 3D ICs. Due to the globalized semiconductor business model, the extended IC supply chain could incur more security challenges on maintaining the integrity, confidentiality, and reliability of integrated circuits and systems. In this work, we analyze the potential security threats induced by the integration techniques for 3D ICs and propose effective attack detection and mitigation methods. More specifically, we first propose a comprehensive characterization for 3D hardware Trojans in the 3D stacking structure. Practical experiment based quantitative analyses have been performed to assess the impact of 3D Trojans on computing systems. Our analysis shows that advanced attackers could exploit the limitation of the most recent 3D IC testing standard IEEE Standard 1838 to bypass the tier-level testing and successfully implement a powerful TSV-Trojan in 3D chips. We propose an enhancement for IEEE Standard 1838 to facilitate the Trojan detection on two neighboring tiers simultaneously. Next, we develop two 3D Trojan detection methods. The proposed frequency-based Trojan-activity identification (FTAI) method can differentiate the frequency changes induced by Trojans from those caused by process variation noise, outperforming the existing time-domain Trojan detection approaches by 38% in Trojan detection rate. Our invariance checking based Trojan detection method leverages the invariance among the 3D communication infrastructure, 3D network-on-chips (NoCs), to tackle the cross-tier 3D hardware Trojans, achieving a Trojan detection rate of over 94%. Furthermore, this work investigates another type of common security threat, side-channel attacks. We first propose to group the supply voltages of different 3D tiers temporally to drive the crypto unit implemented in 3D ICs such that the noise in power distribution network (PDN) can be induced to obfuscate the original power traces and thus mitigates correlation power analysis (CPA) attacks. Furthermore, we study the side-channel attack on the logic locking mechanism in monolithic 3D ICs and propose a logic-cone conjunction (LCC) method and a configuration guideline for the transistor-level logic locking to strengthen its resilience against CPA attacks

Integrating simultaneous bi-direction signalling in the test fabric of 3D stacked integrated circuits.

Jennions, Ian K. - Associate SupervisorThe world has seen significant advancements in electronic devices’ capabilities, most notably the ability to embed ultra-large-scale functionalities in lightweight, area and power-efficient devices. There has been an enormous push towards quality and reliability in consumer electronics that have become an indispensable part of human life. Consequently, the tests conducted on these devices at the final stages before these are shipped out to the customers have a very high significance in the research community. However, researchers have always struggled to find a balance between the test time (hence the test cost) and the test overheads; unfortunately, these two are inversely proportional. On the other hand, the ever-increasing demand for more powerful and compact devices is now facing a new challenge. Historically, with the advancements in manufacturing technology, electronic devices witnessed miniaturizing at an exponential pace, as predicted by Moore’s law. However, further geometric or effective 2D scaling seems complicated due to performance and power concerns with smaller technology nodes. One promising way forward is by forming 3D Stacked Integrated Circuits (SICs), in which the individual dies are stacked vertically and interconnected using Through Silicon Vias (TSVs) before being packaged as a single chip. This allows more functionality to be embedded with a reduced footprint and addresses another critical problem being observed in 2D designs: increasingly long interconnects and latency issues. However, as more and more functionality is embedded into a small area, it becomes increasingly challenging to access the internal states (to observe or control) after the device is fabricated, which is essential for testing. This access is restricted by the limited number of Chip Terminals (IC pins and the vertical Through Silicon Vias) that a chip could be fitted with, the power consumption concerns, and the chip area overheads that could be allocated for testing. This research investigates Simultaneous Bi-Directional Signaling (SBS) for use in Test Access Mechanism (TAM) designs in 3D SICs. SBS enables chip terminals to simultaneously send and receive test vectors on a single Chip Terminal (CT), effectively doubling the per-pin efficiency, which could be translated into additional test channels for test time reduction or Chip Terminal reduction for resource efficiency. The research shows that SBS-based test access methods have significant potential in reducing test times and/or test resources compared to traditional approaches, thereby opening up new avenues towards cost-effectiveness and reliability of future electronics.PhD in Manufacturin

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity