Fiber weave skew and copper roughness:effects on transmission line performance on PCB

Abstract. Designing manufacturable high performing transmission lines is an essential part of modern electronics design work. This thesis focuses on interconnect design and simulation while also examining how materials and manufacturing affects the designed interconnect. The goal of this work is to find how big and what kind of effects different design and manufacturing variables have and how to be mindful of all the relevant factors during the design phase. Specific focus areas are fiber weave effect and losses caused by copper roughness. In this thesis theory behind transmission lines on PCB is outlined first along with different material properties and relevant material test methods. Effects of different design parameters and material properties are then examined through simulations and literature. Accurate simulation of fiber weave skew with readily available simulation tools is difficult, but fiber weave skew itself can be mitigated with design choices. Copper roughness can be modelled with various models. Multiple different ways to represent copper roughness in the scope of PCB design exist. These various roughness representations are examined extensively through examples. Copper roughness was found to have significant effects on signal integrity and different roughness models were found to perform very differently.Lasipunosajoitusvääristymän ja kuparin karkeuden vaikutukset siirtolinjojen suorituskykyyn piirilevyllä. Tiivistelmä. Modernin elektroniikkasuunnittelun yksi keskeisistä osista on massatuotantokelpoisten korkean suorituskyvyn, siirtolinjojen suunnittelu. Tämä diplomityö keskittyy yhteyssuunnitteluun ja siirtolinjarakenteiden simulointiin piirilevyllä. Valmistusprosessien ja materiaalien vaikutuksia siirtolinjoihin tarkastellaan myös. Työn tavoitteena on selvittää Kuinka paljon ja millaisia vaikutuksia eri suunnittelu- ja materiaalivalinnoilla on sekä miten suunnittelija voi parhaiten ottaa eri seikat huomioon suunnittelun eri vaiheissa. Tarkemmin tarkasteltavat ilmiöt ovat kuparin pinnan karkeuden aiheuttamat häviöt ja piirilevyn eristemateriaalin lasikuitupunosrakenteen aiheuttama ajoitusvääristymä. Teoria piirilevyllä oleville siirtolinjoille on esitelty erilaisten materiaaliominaisuuksien ja materiaalien testausmenetelmien ohella ensin. Teoriaosuuden jälkeen eri suunnitteluparametrien ja materiaaliominaisuuksien vaikutuksia tutkitaan simulaatioiden ja kirjallisuuden pohjalta. Lasipunosajoitusvääristymän simulointi helposti saatavilla olevilla simulointityökaluilla on haasteellista, mutta ilmiön aiheuttamia vaikutuksia on mahdollista pienentää erilaisilla suunnitteluratkaisuilla. Kuparin karkeuden mallintamiseen on tarjolla useita erilaisia simulointimalleja. Lisäksi kuparin karkeus voidaan esittää usealla eri tavalla. Erilaisia kuparin karkeuden esitystapoja piirilevykontekstissa on tarkasteltu kattavasti esimerkkien kautta. Kuparin karkeuden todettiin vaikuttavan signaalien vaimentumiseen merkittävästi ja eri karkeusmallien huomattiin palauttavan huomattavasti toisistaan poikkeavia tuloksia

Carbon Doped Silicon Dioxide Low K Dielectric Material.[QC585.75.S55 L732 2004 f rb][Microfiche 7649]

Objektif kajian ini adalah untuk mengkaji keberkesanan mendopkan sebatian karbon keatas SiO2 untuk menghasilkan bahan dielektrik k rendah. The semiconductor industry is entering a new millennium where scientists and engineers are continuing to search for the ideal dielectric material for future chip fabrication

An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction

In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper

The Automated Array Assembly Task of the Low-cost Silicon Solar Array Project, Phase 2

An advanced process sequence for manufacturing high efficiency solar cells and modules in a cost-effective manner is discussed. Emphasis is on process simplicity and minimizing consumed materials. The process sequence incorporates texture etching, plasma processes for damage removal and patterning, ion implantation, low pressure silicon nitride deposition, and plated metal. A reliable module design is presented. Specific process step developments are given. A detailed cost analysis was performed to indicate future areas of fruitful cost reduction effort. Recommendations for advanced investigations are included

DESIGN, MODELING, OPTIMIZATION, AND BENCHMARKING OF INTERCONNECTS AND SCALING TECHNOLOGIES AND THEIR CIRCUIT AND SYSTEM LEVEL IMPACT

This research focuses on the future of integrated circuit (IC) scaling technologies at the device and back end of line (BEOL) level. This work includes high level modeling of different technologies and quantifying potential performance gains on a circuit and system level. From the device side, this research looks at the scaling challenges and the future scaling drivers for conventional charge-based devices implemented at the 7nm technology node and beyond. It examines the system-level performance of stacking device logic in addition to tunneling field effect transistors (TFET) and their potential as beyond-CMOS devices. Finally, this research models and benchmarks BEOL scaling challenges and evaluates proposed technological advancements such as metal barrier scaling for copper interconnects and replacing local interconnects with ruthenium. Potential impact on performance, power, and area of these interconnect technologies is quantified for fully placed and routed circuits.Ph.D

Application of effective medium theory to the analysis of integrated circuit interconnects

The design and physical verification of contemporary integrated circuits is a challenging task due to their complexity. System-in-Package is an example of generally congested electronic components and interconnects which in the initial design process rely on computationally intensive electromagnetic simulations. Hence the available computer memory capacity and computational speed become meaningful limitations. An alternative method which allows the designer to overcome or reduce the limits is desired. This work represents the first demonstration of the application of effective medium theory to the analysis of those segments of the entire integrated system where the interconnect networks are more dense. The presented approach takes advantage of the deep subwavelength characteristic of interconnect structures. In order to achieve the aim of defining the homogeneous equivalent for the interconnect grating structure a few steps were followed towards proving the homogenisation concept and finally presenting it by an analytical formulation. A set of parameters (metal fill factor, aspect ratio, dielectric background and period-to-wavelength ratio) with values related to typical design rules were considered. Relating these parameters allows the empirical models to be defined. In order to show the relationship between existing effective medium theories and those developed in this Thesis, the presented empirical models are defined in terms of the Maxwell-Garnett mixing rule with an additional scaling factor. The distribution of the scaling factor was analysed in terms of the calculated reflection and transmission coefficients of the homogenised structures that are equivalent to a given grating geometry. Finally the scaling factor, for each empirical model, was expressed by an analytical formula and the models validated by their application to the numerical analysis of grating structures. The numerical validation was carried out by comparing the reflection and transmission coefficients obtained for the detailed and homogenised structures. In order to ensure the empirical models can be broadly employed, the performance of the model in the presence of non-normally incident plane wave was evaluated. For the range of angles ±30º the model is accurate to 5%. The impact of the shape of the grating, specifically the case of a tapered profile, typical of actual fabricated interconnects was also considered, with sidewall tapers of up to 5º giving the same error not higher than 5%. Experimental validation of the application of the homogenisation concept to the analysis of interconnects is desired for two main applications: for the reflectivity estimation of a whole chip in a System-in-Package and for the performance estimation of interconnects on lower metal layers in an interconnect stack. For the first, free-space measurements are taken of a grating plate with copper rods aligned in parallel illuminated by a plane wave in the X-band (8.2-12.4 GHz). For the second, S-parameters are measured for microstrip waveguides with a number of metal rods embedded in the substrate between the signal line and ground plane. The good agreement with the simulations validates the homogenisation approach for the analysis of interconnects

Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect

This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an alternative to the existing Cu-based interconnect for post-CMOS technology nodes with an emphasis on thermal stability. Starting from the material modeling, this work includes material characterization, exploration of electronic properties, vibrational properties and to analyze performance as a VLSI interconnect. Using state of the art density functional theories (DFT) one-dimensional and two-dimensional materials were designed for exploring their electronic structures, transport properties and their circuit behaviors. Primarily carbon nanotube (CNT), graphene and graphene/copper based interconnects were studied in this work. Being reduced dimensional materials the charge carriers in CNT(1-D) and in graphene (2-D) are quantum mechanically confined as a result of this free electron approximation fails to explain their electronic properties. For same reason Drude theory of metals fails to explain electronic transport phenomena. In this work Landauer transport theories using non-equilibrium Green function (NEGF) formalism was used for carrier transport calculation. For phonon transport studies, phenomenological Fourier’s heat diffusion equation was used for longer interconnects. Semi-classical BTE and Landauer transport for phonons were used in cases of ballistic phonon transport regime. After obtaining self-consistent electronic and thermal transport coefficients, an equivalent circuit model is proposed to analyze interconnects’ electrical performances. For material studies, CNTs of different variants were analyzed and compared with existing copper based interconnects and were found to be auspicious contenders with integrational challenges. Although, Cu based interconnect is still outperforming other emerging materials in terms of the energy-delay product (1.72 fJ-ps), considering the electromigration resistance graphene Cu hybrid interconnect proposed in this dissertation performs better. Ten times more electromigration resistance is achievable with the cost of only 30% increase in energy-delay product. This unique property of this proposed interconnect also outperforms other studied alternative materials such as multiwalled CNT, single walled CNT and their bundles

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

The high frequency electrical properties of interconnects on a flexible polyimide substrate including the effects of humidity

Flexible circuit board materials can be used to advantage in radio frequency and high-speed digital systems but an obstacle to their use is the lack of availability of information on the electrical properties of materials to high frequencies and, in particular, the variation in dielectric constant and loss tangent as a function of frequency. This makes accurate electromagnetic simulation of high frequency flexible interconnects difficult. The variation of the electrical properties of these materials as a function of environmental parameters, such as humidity, is also unknown at higher frequencies. This paper has, using microwave resonators, investigated the electrical properties from 2 GHz to 18 GHz of a polyimide flexible circuit board material saturated at 25% RH and at 85% RH relative humidity levels. Rigid circuit board materials FR4 and CER-10 were also measured as reference materials. The relative permittivity, epsilon(r), total loss, alpha(T), and loss tangent, tan delta, have been extracted from the measurements for each material. The strong influence of conductor losses on overall losses when using thin materials such as flex at high frequency has also been evaluated and quantified in these measurements. In addition to the resonators used for measurement of material electrical properties, microstrip transmission lines were also included on each test sample and their s-parameters were measured at the same time and under the same conditions as the resonators. Comparisons between the measured electrical performance of the microstrip transmission lines and simulations of the lines based on the extracted material parameters show a high degree of correlation, indicating the validity of both the use of the resonator approach and overall loss measurement methodologies