Very large time constant Gm-C Filters

In this study a set of tools for the design of fully integrated transconductor-capacitor (Gm-C) filters, with very large time constants and current consumption under one micro-Ampere are presented. The selected application is a 2nd order bandpass-filter-amplifier, with a gain of 400 from 0.5 to 7Hz, carrying out the signal conditioning of a piezoelectric accelerometer which is part of an implantable cardiac pacemaker. The main challenge is to achieve very large time constants, without using any discrete external component. The chosen circuit technique to fulfill the requirement is series-parallel current division applied to standard symmetrical transconductors (OTAs). These circuits have demonstrated to be an excellent solution regarding their occupied area, power consumption, noise, linearity, and particularly offset. OTAs as low as 33pS -equivalent to a 30G resistor-, with up to 1V linear range, and input referred offset of a few mV, were designed, fabricated in a standard 0.8 micron CMOS technology, and tested. The application requires the series-parallel association of a large number of transistors, and the use of bias currents as low as a few pico-Amperes, which is not very common in analog integrated circuits. In this case the designer should employ maximum care in the selection of the transistor models to be used. A central aspect of this thesis was also to evaluate and develop noise and offset estimation models which was not obvious in the very beginning of the research. In the first two chapters an introduction to the target application is presented, and several MOS transistor characteristics in terms of the inversion coefficient -using the ACM transistor model- are evaluated. In chapter 3 it is discussed whether the usual flicker and thermal noise models are consistent regarding series-parallel association, and adequately represent the expected noise behavior under different bias conditions. A consistent, physics-based, one-equation-all-regions model for flicker noise in the MOS transistor is then presented. Several noise measurements are included demonstrating that the new model accurately fits widely different bias situations. A new model for mismatch offset in MOS transistors is presented, as a corollary of the flicker noise analysis. Finally, the correlation between flicker noise and mismatch offset, that can be seen as a DC noise, is shown. In chapter 4, the design of OTAs with an extended linear range, and very low transconductance, using series-parallel current division is presented. Precise tools are introduced for the estimation of noise and mismatch offset in series-parallel current mirrors, that are shown to help in the reduction of inaccuracies in the copy of currents with a large copy factor. The design and measurement of several OTA examples are presented. In chapter 5, the developed tools, and the OTAs shown, are employed in the design of the above mentioned filter for the piezoelectric accelerometer. A general methodology for the design of Gm-C filters with similar characteristics is established. The filter was fabricated and tested, successfully operating with a total power consumption of 233nA, up to a 2V power supply, with an input noise and mismatch offset of 2-4 Vrms, and 18 V respectively. To summarize the main results obtained were: The development of a new flicker noise model, the study of the effect of mismatch regarding series-parallel association, a new design methodology for OTAs and Gm-C filters. It is our hope that this constitutes a helpful set of tools for the circuit designer.En esta tesis se presenta un conjunto de herramientas para el diseño de circuitos integrados que implementan filtros transconductor-capacitor (Gm-C), de muy altas constantes de tiempo, con bajo ruido, y consumo de corriente por debajo del micro-Ampere. Como ejemplo de aplicación se toma un amplificador-pasabanda 2º orden, de ganancia 400 en la banda de 0.5 a 7Hz, que realiza el acondicionamiento de señal de un acelerómetro piezoeléctrico a ser empleado en un marcapasos implantable. El principal desafío es realizar en dicho filtro de tiempo continuo, muy altas constantes de tiempo sin usar componentes externos. La técnica elegida para alcanzar tal objetivo es la división serie-paralelo de corriente en transconductores (OTAs) simétricos estándar. Estos circuitos demostraron ser una excelente solución en cuanto al área ocupada, su consumo, ruido, linealidad, y en particular offset. Se diseñaron, fabricaron, y midieron, OTAs hasta 33pS -equivalente a una resistencia de 30G -, con hasta 1V de rango de lineal, y offset a la entrada de algunos mV, utilizando una tecnología CMOS de 0.8 micras de largo mínimo de canal. La aplicación requiere la asociación serie-paralelo de un gran número de transistores, y polarización con corrientes de hasta pico-Amperes, lo que constituye una situación poco frecuente en circuitos integrados analógicos. En este marco el diseñador debe elegir los modelos de transistor con sumo cuidado. Un aspecto central de esta tesis es también, el estudio y presentación de modelos adecuados de ruido y offset, que no resultan obvios al principio. En los primeros dos capítulos se realiza una introducción y se revisa, utilizando el modelo ACM, diferentes características del transistor MOS en función del nivel de inversión. En el capítulo 3 revisa la pertinencia y consistencia frente a la asociación serie-paralelo, de los modelos usuales de ruido de flicker o 1/f, y térmico. Luego se presenta, incluyendo medidas, un nuevo modelo físico, consistente, simple, y válido en todas las regiones de operación del transistor MOS, para el ruido de flicker. Como corolario a este estudio se presenta un nuevo modelo para estimar el desapareo entre transistores, en función no solo de la geometría, pero también de la polarización. Se demuestra la correlación, debido a su origen físico análogo, entre el ruido de flicker y el offset por desapareo que puede ser visto como un ruido en DC. En el capítulo 4 se presenta el diseño de OTAs con rango de linealidad extendido, y muy baja transconductancia, utilizando división serie-paralelo de corriente. Se presentan herramientas precisas para la estimación de offset y ruido y se demuestra la utilidad de la técnica para reducir el offset en espejos de corriente. Se presenta el diseño y medida de diversos OTAs. En el capítulo 5, las herramientas desarrolladas, y los OTAs presentados, son empleados en el diseño del filtro descripto para un acelerómetro piezoeléctrico. Se establece una metodología general para el diseño de filtros Gm-C con características similares. El filtro se fabricó y midió, operando en forma satisfactoria, con un consumo total de 230nA y hasta los 2V de tensión de alimentación, con ruido y offset a la entrada de tan solo 2-4 Vrms, y 18 V respectivamente. El desarrollo de un nuevo modelo de ruido 1/f para el transistor MOS, el estudio de la influencia del offset frente a la asociación serie-paralelo y su aplicación en OTAs, la metodología de diseño empleada, la demostración del uso de técnicas novedosas en una aplicación como la elegida que tiene relevancia tecnológica e interés académico; esperamos que todo ello constituya una contribución valiosa para la comunidad científica en microelectrónica y un conjunto de herramientas de utilidad para el diseño de circuitos

A novel switched capacitor frequency tuning technique for continuous-time Gm-C filters

A novel approach for the automatic frequency tuning of Continuous Time Filters is presented. This approach is based on a switched capacitor circuit and only needs three capacitors, some switches and a replica transconductor to adjust the pole frequency of the filter. Despite the simplicity of the scheme, the accuracy of the proposed system is under 1% of frequency error. To evaluate the idea a version of the circuit has been designed in a 0.5 µm CMOS technology with a 3.3 V power supply and simulation results are provided

Comparison of the DR of continuous time Gm-C filters using different structures

Comunicación presentada al "ICC'06" celebrada en Atenas del 10 al 12 de Julio del 2006.This paper presents design techniques to evaluate the noise and distortion of continuous time Gm-C filters. Also presents techniques to improve the dynamic range of such filters keeping a relation of integer numbers between the transconductors. Furthermore the comparison of the dynamic range for the same power using different structures is presented.This work has been partially funded by the Spanish MCyT under Project TIC2003-02355 (RAICONIF).Peer Reviewe

An auto-biased 0.5 um CMOS transconductor for very high frequency applications

This paper describes a CMOS transconductance cell for the implementation of very high frequency current-mode gm-C filters. It features simple pseudo-differential circuitry employing small device size transistors and yielding a power dissipation of less than 1 mW/pole at nominal 3.0 V supply voltage. Self-biased common-mode voltage designed to minimize mismatch errors, improves noise and stability behavior. Short channel effects are analyzed and simulation results are presented

A bipolar, semi-gaussian pulse shaping amplifier based on transconductance-C continuous time filters for use in a high resolution, small animal x-ray CT system

A new bipolar, semi-gaussian pulse shaping amplifier using transconductance-C (Gm-C) filters has been developed for use with the Oak Ridge National Laboratory (ORNL) MicroCAT small animal x-ray CT imaging system. The MicroCAT system employs Cadmium Zinc Telluride (CZT), a relatively new semiconductor detector material. The pulse shaping amplifier is based on a Gm-C filter topology and has adjustable gain, tunable filter time constants and quality factors as well as a differential signal path. The transconductor circuit design is also presented with emphasis placed upon the noise and linearity of the circuit. The architecture and experimental results for the prototype pulse shaping amplifier are also presented. The prototype was fabricated in the 1.2μ AMI NWELL CMOS process through the MOSIS program

0.13-µm CMOS tunable transconductor based on the body-driven gain boosting technique with application in Gm-C filters

We present a low-voltage low-power CMOS tunable transconductor exploiting body gain boosting to increase the small-signal output resistance. As a distinctive feature, the proposed scheme allows the OTA transconductance to be tuned via the current biasing the gain-boosting circuit. The proposed transconductor has been designed in a 0.13-µm CMOS technology and powered from a 1.2-V supply. To show a possible application, a 0.5-MHz tunable third order Chebyshev low pass filter suitable for the Ultra Low Power Bluetooth Standard has been designed. The filter simulations show that all the requirements of the chosen standard are met, with good performance in terms of linearity, noise and power consumption

0.5V 3rd-order Tunable gm-C Filter

This paper proposes a 3rd-order gm-C filter that operates with the extremely low voltage supply of 0.5V. The employed transconductor is capable for operating in an extremely low voltage power supply environment. A benefit offered by the employed transconductor is that the filter’s cut-off frequency can be tuned, through a dc control current, for relatively large ranges. The filter structure was designed using normal threshold transistors of a triple-well 0.13μm CMOS process and is operated under a 0.5V supply voltage; its behavior has been evaluated through simulation results by utilizing the Analog Design Environment of the Cadence software

A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter

This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated filters. The presented approach is based on Volterra's series theory and matrix algebra manipulation. This procedure has been integrated in a constrained optimization routine to improve the dynamic range of the filter while keeping the area and power consumption at a minimum. The proposed approach is demonstrated with the design, from system- to physical-level, of a seventh-order low-pass continuous-time elliptic filter for a high-performance broadband power-line communication receiver. The filter shows a nominal cut-off frequency of fc = 34MHz, less than 1dB ripple in the pass-band, and a maximum stop-band rejection of 65dB. Additionally, the filter features 12dB programmable boost in the pass-band to counteract high frequency components attenuation. Taking into account its wideband transfer characteristic, the filter has been implemented using G m-C techniques. The basic building block of its structure, the transconductor, uses a source degeneration topology with local feedback for linearity improving and shows a worst-case intermodulation distortion of -70 dB for two tones close to the passband edge, separated by 1MHz, with 70mV of amplitude. The filter combines very low noise (peak root spectral noise density below 56nV/√Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5Vpp amplitude) properties. The filter has been designed in a 0.18μm CMOS technology and it is compliant with industrial operation conditions (-40 to 85°C temperature variation and ±5% power supply deviation). The filter occupies 13mm2 and exhibits a typical power consumption of 450 mW from a 1.8V voltage supply.Ministerio de Ciencia y Tecnología TIC2003-0235

Low power architecture and circuit techniques for high boost wideband Gm-C filters

With the current trend towards integration and higher data rates, read channel design needs to incorporate significant boost for a wider signal bandwidth. This dissertation explores the analog design problems associated with design of such 'Equalizing Filter' (boost filter) for read channel applications. Specifically, a 330MHz, 5th order Gm-C continuous time lowpass filter with 24dB boost is designed. Existing architectures are found to be unsuitable for low power, wideband and high boost operation. The proposed solution realizes boosting zeros by efficiently combining available transfer functions associated with all nodes of cascaded biquad cells. Further, circuit techniques suitable for high frequency filter design are elaborated such as: application of the Gilbert cell as a variable transconductor and a new Common-Mode-Feedback (CMFB) error amplifier that improves common mode accuracy without compromising on bandwidth or circuit complexity. A prototype is fabricated in a standard 0.35mm CMOS process. Experimental results show -41dB of IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation

System-level optimization of baseband filters for communication applications

In this paper, a design approach for the high-level synthesis of programmable continuous-time baseband filters able to achieve optimum trade-off among dynamic range, distortion behavior, mismatch tolerance and power area consumptions is presented. The proposed approach relies on building programming circuit elements as arrays of switchable unit cells and defines the synthesis as a constrained optimization problem with both continuous and discrete variables, this last representing the number of enabled cells of the arrays at each configuration. The cost function under optimization is, then, defined as a weighted combination of performance indices which are estimated from macromodels of the circuit elements. The methodology has been implemented in MATLAB™ and C++, and covers all the classical approximation techniques for filters, most common circuit topologies (namely, ladder simulation and cascaded biquad realizations) and both transconductance-C (Gm-C) and active-RC implementation approaches. The proposed synthesis strategy is illustrated with a programmable equal-ripple ladder Gm-C filter for a multi-band power-line communication modem.P.R.O.F.I.T. FIT-070000-2001-84