Impact of non uniform strain configuration on transport properties for FD14+ devices

As device dimensions are scaled down, the use of non-geometrical performance boosters becomes of special relevance. In this sense, strained channels are proposed for the 14 nm FDSOI node. However this option may introduce a new source of variability since strain distribution inside the channel is not uniform at such scales. In this work, a MS-EMC study of different strain configurations including non-uniformities is presented showing drain current degradation because of the increase of intervalley phonon scattering and the subsequent variations of transport effective mass and drift velocity. This effect, which has an intrinsic statistical origin, will make necessary further optimizations to keep the expected boosting capabilities of strained channels

Modeling and Simulation of Subthreshold Characteristics of Short-Channel Fully-Depleted Recessed-Source/Drain SOI MOSFETs

Non-conventional metal-oxide-semiconductor (MOS) devices have attracted researchers‟ attention for future ultra-large-scale-integration (ULSI) applications since the channel length of conventional MOS devices approached the physical limit. Among the non-conventional CMOS devices which are currently being pursued for the future ULSI, the fully-depleted (FD) SOI MOSFET is a serious contender as the SOI MOSFETs possess some unique features such as enhanced short-channel effects immunity, low substrate leakage current, and compatibility with the planar CMOS technology. However, due to the ultra-thin source and drain regions, FD SOI MOSFETs possess large series resistance which leads to the poor current drive capability of the device despite having excellent short-channel characteristics. To overcome this large series resistance problem, the source/drain area may be increased by extending S/D either upward or downward. Hence, elevated-source/drain (E-S/D) and recessed-source/drain (Re-S/D) are the two structures which can be used to minimize the series resistance problem. Due to the undesirable issues such as parasitic capacitance, current crowding effects, etc. with E-S/D structure, the Re-S/D structure is a better choice. The FD Re-S/D SOI MOSFET may be an attractive option for sub-45nm regime because of its low parasitic capacitances, reduced series resistance, high drive current, very high switching speed and compatibility with the planar CMOS technology. The present dissertation is to deal with the theoretical modeling and computer-based simulation of the FD SOI MOSFETs in general, and recessed source/drain (Re-S/D) ultra-thin-body (UTB) SOI MOSFETs in particular. The current drive capability of Re-S/D UTB SOI MOSFETs can be further improved by adopting the dual-metal-gate (DMG) structure in place of the conventional single-metal-gate-structure. However, it will be interesting to see how the presence of two metals as gate contact changes the subthreshold characteristics of the device. Hence, the effects of adopting DMG structure on the threshold voltage, subthreshold swing and leakage current of Re-S/D UTB SOI MOSFETs have been studied in this dissertation. Further, high-k dielectric materials are used in ultra-scaled MOS devices in order to cut down the quantum mechanical tunneling of carriers. However, a physically thick gate dielectric causes fringing field induced performance degradation. Therefore, the impact of high-k dielectric materials on subthreshold characteristics of Re-S/D SOI MOSFETs needs to be investigated. In this dissertation, various subthreshold characteristics of the device with high-k gate dielectric and metal gate electrode have been investigated in detail. Moreover, considering the variability problem of threshold voltage in ultra-scaled devices, the presence of a back-gate bias voltage may be useful for ultimate tuning of the threshold voltage and other characteristics. Hence, the impact of back-gate bias on the important subthreshold characteristics such as threshold voltage, subthreshold swing and leakage currents of Re-S/D UTB SOI MOSFETs has been thoroughly analyzed in this dissertation. The validity of the analytical models are verified by comparing model results with the numerical simulation results obtained from ATLAS™, a device simulator from SILVACO Inc

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology is facing great challenges to overcome severe short-channel effects. Multigate MOSFETs are one of the most promising candidates for scaling beyond Si CMOS, due to better electrostatic control as compared to conventional planar MOSFETs. Conventional dry etching-induced surface damage is one of the main sources of performance degradation for multigate transistors, especially for III-V high mobility materials. It is also challenging to increase the fin aspect ratio by dry etching because of the non-ideal anisotropic etching profile. Here, we report a novel method, inverse metal-assisted chemical etching (i-MacEtch), in lieu of conventional RIE etching, for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, allowing for the fabrication of InP fin channels with atomically smooth sidewalls. The sidewall features resulting from this unique and simplified process ensure high interface quality between high-k dielectric layer and InP fin channel. Experimental and theoretical analyses show that high-aspect-ratio FinFETs, which could deliver more current per area under much relaxed horizontal geometry requirements, are promising in pushing the technology node ahead where conventional scaling has met its physical limits. The performance of the FinFET was further investigated through numerical simulation. A new kind of FinFET with asymmetric gate and source/drain contacts has been proposed and simulated. By benchmarking with conventional symmetric FinFET, better short-channel behavior with much higher current density is confirmed. The design guidelines are provided. The overall circuit delay can be minimized by optimizing gate lengths according to different local parasites among circuits in interconnection-delay-dominated SoC applications. Continued transistor scaling requires even stronger gate electrostatic control over the channel. The ultimate scaling structure would be gate-all-around nanowire MOSFETs. We demonstrate III-V junctionless gate-all-around (GAA) nanowire (NW) MOSFETs for the first time. For the first time, source/drain (S/D) resistance and thermal budget are minimized by regrowth using metalorganic chemical vapor deposition (MOCVD) in III-V MOSFETs. The fabricated short-channel (Lg=80 nm) GaAs GAA NWFETs with extremely narrow nanowire width (WNW= 9 nm) show excellent transconductance (gm) linearity at biases (300 mV), characterized by the high third intercept point (2.6 dBm). The high linearity is especially important for low power applications because it is insensitive to bias conditions

III-V and 2D Devices: from MOSFETs to Steep-Slope Transistors

With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel device structures have been extensively studied and attracted a lot of attention in solid-state device research. In this dissertation, solid-state electron devices for post-Si CMOS applications are explored including both new materials such as III-V and 2D materials and new device structures such as tunneling field-effect transistors and negative capacitance field-effect transistors. Multiple critical challenges in applying such new materials and new device structures are addressed and the key achievements in this dissertation are summarized as follows: 1) Development of fabrication process technology for ultra-scaled planar and 3D InGaAs MOSFETs. 2) Interface passivation by forming gas anneal on InGaAs gate-all-around MOSFETs. 3) Characterization methods for ultra-scaled MOSFETs, including a correction to subthreshold method and low frequency noise characterization in short channel devices. 4) Development of short channel InGaAs planar and 3D gate-allaround tunneling field-effect transistors. 5) Negative capacitance field-effect transistors with hysteresis-free and bi-directional sub-thermionic subthreshold slope and the integration with various channel materials such as InGaAs and MoS2

Technology stragegy and business development at a semiconductor equipment company : a process definition and case study of a new technology

Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering; in conjunction with the Leaders for Manufacturing Program at MIT, 2002.Includes bibliographical references (p. 96-100).by Christopher Lance Durham.S.M.M.B.A

Strain integration and performance optimization in sub-20nm FDSOI CMOS technology

La technologie CMOS à base de Silicium complètement déserté sur isolant (FDSOI) est considérée comme une option privilégiée pour les applications à faible consommation telles que les applications mobiles ou les objets connectés. Elle doit cela à son architecture garantissant un excellent comportement électrostatique des transistors ainsi qu'à l'intégration de canaux contraints améliorant la mobilité des porteurs. Ce travail de thèse explore des solutions innovantes en FDSOI pour nœuds 20nm et en deçà, comprenant l'ingénierie de la contrainte mécanique à travers des études sur les matériaux, les dispositifs, les procédés d'intégration et les dessins des circuits. Des simulations mécaniques, caractérisations physiques (µRaman), et intégrations expérimentales de canaux contraints (sSOI, SiGe) ou de procédés générant de la contrainte (nitrure, fluage de l'oxyde enterré) nous permettent d'apporter des recommandations pour la technologie et le dessin physique des transistors en FDSOI. Dans ce travail de thèse, nous avons étudié le transport dans les dispositifs à canal court, ce qui nous a amené à proposer une méthode originale pour extraire simultanément la mobilité des porteurs et la résistance d'accès. Nous mettons ainsi en évidence la sensibilité de la résistance d'accès à la contrainte que ce soit pour des transistors FDSOI ou nanofils. Nous mettons en évidence et modélisons la relaxation de la contrainte dans le SiGe apparaissant lors de la gravure des motifs et causant des effets géométriques (LLE) dans les technologies FDSOI avancées. Nous proposons des solutions de type dessin ainsi que des solutions technologiques afin d'améliorer la performance des cellules standard digitales et de mémoire vive statique (SRAM). En particulier, nous démontrons l'efficacité d'une isolation duale pour la gestion de la contrainte et l'extension de la capacité de polarisation arrière, qui un atout majeur de la technologie FDSOI. Enfin, la technologie 3D séquentielle rend possible la polarisation arrière en régime dynamique, à travers une co-optimisation dessin/technologie (DTCO).The Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization

Etude des transistors MOSFET à barrière Schottky, à canal Silicium et Germanium sur couches minces

Until the early 2000’s Dennard’s scaling rules at the transistor level have enabled to achieve a performance gain while still preserving the basic structure of the MOSFET building block from one generation to the next. However, this conservative approach has already reached its limits as shown by the introduction of channel stressors for the sub-130 nm technological nodes, and later high-k/metal gate stacks for the sub-65 nm nodes. Despite the introduction of high-k gate dielectrics, constraints in terms of gate leakage and reliability have been delaying the diminution of the equivalent oxide thickness (EOT). Concurrently, lowering the supply voltage (VDD) has become a critical necessity to reduce both the active and passive power density in integrated circuits. Hence the challenge: how to keep decreasing both gate length and supply voltage faster than the EOT without losing in terms of ON-state/OFF-state performance trade-off? Several solutions can be proposed aiming at solving this conundrum for nanoscale transistors, with architectures in rupture with the plain old Silicon-based MOSFET with doped Source and Drain invented in 1960. One approach consists in achieving an ION increase while keeping IOFF (and Vth) mostly unchanged. Specifically, two options are considered in detail in this manuscript through a review of their respective historical motivations, state-of-the-art results as well as remaining fundamental (and technological) challenges: i/ the reduction of the extrinsic parasitic resistance through the implementation of metallic Source and Drain (Schottky Barrier FET architecture); ii/ the reduction of the intrinsic channel resistance through the implementation of Germanium-based mobility boosters (Ge CMOS, compressively-strained SiGe channels, n-sSi/p-sSiGe Dual Channel co-integration). In particular, we study the case of thin films on insulator (SOI, SiGeOI, GeOI substrates), a choice justified by: the preservation of the electrostatic integrity for the targeted sub-22nm nodes; the limitation of ambipolar leakage in SBFETs; the limitation of junction leakage in (low-bandgap) Ge-based FETs. Finally, we show why, and under which conditions the association of the SBFET architecture with a Ge-based channel could be potentially advantageous with respect to conventional Si CMOS.Jusqu’au début des années 2000, les règles de scaling de Dennard ont permis de réaliser des gains en performance tout en conservant la structure de la brique de base transistor d’une génération technologique à la suivante. Cependant, cette approche conservatrice a d’ores et déjà atteint ses limites, comme en témoigne l’introduction de la contrainte mécanique pour les générations sub-130nm, et les empilements de grille métal/high-k pour les nœuds sub-65nm. Malgré l’introduction de diélectriques à forte permittivité, des limites en termes de courants de fuite de grille et de fiabilité ont ralenti la diminution de l’épaisseur équivalente d’oxyde (EOT). De façon concommitante, la diminution de la tension d’alimentation (VDD) est devenue une priorité afin de réduire la densité de puissance dissipée dans les circuits intégrés. D’où le défi actuel: comment continuer de réduire à la fois la longueur de grille et la tension d’alimentation plus rapidement que l’EOT sans pour autant dégrader le rapport de performances aux états passant et bloqué (ON et OFF) ? Diverses solutions peuvent être proposées, passant par des architectures s’éloignant du MOSFET conventionnel à canal Si avec source et drain dopés tel que défini en 1960. Une approche consiste en réaliser une augmentation du courant passant (ION) tout en laissant le courant à l’état bloqué (IOFF) et la tension de seuil (Vth) inchangés. Concrètement, deux options sont considérées en détail dans ce manuscrit à travers une revue de leurs motivations historiques respectives, les résultats de l’état de l’art ainsi que les obstacles (fondamentaux et technologiques) à leur mise en œuvre : i/ la réduction de la résistance parasite extrinsèque par l’introduction de source et drain métalliques (architecture transistor à barrière Schottky) ; ii/ la réduction de la résistance de canal intrinsèque par l’introduction de matériaux à haute mobilité à base de Germanium (CMOS Ge, canaux SiGe en contrainte compressive, co-intégration Dual Channel n-sSi/p-sSiGe). En particulier, nous étudions le cas de couches minces sur isolant (substrats SOI, SiGeOI, GeOI), un choix motivé par: la préservation de l’intégrité électrostatique pour les nœuds technologiques sub-22nm; la limitation du courant de fuite ambipolaire dans les SBFETs; la limitation du courant de fuites de jonctions dans les MOSFETs à base de Ge (qui est un matériau à faible bandgap). Enfin, nous montrons pourquoi et dans quelles conditions l’association d’une architecture SBFET et d’un canal à base de Germanium peut être avantageuse vis-à-vis du CMOS Silicium conventionnel

Modelling and simulation study of NMOS Si nanowire transistors

Nanowire transistors (NWTs) represent a potential alternative to Silicon FinFET technology in the 5nm CMOS technology generation and beyond. Their gate length can be scaled beyond the limitations of FinFET gate length scaling to maintain superior off-state leakage current and performance thanks to better electrostatic control through the semiconductor nanowire channels by gate-all-around (GAA) architecture. Furthermore, it is possible to stack nanowires to enhance the drive current per footprint. Based on these considerations, vertically-stacked lateral NWTs have been included in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) to allow for further performance enhancement and gate pitch scaling, which are key criteria of merit for the new CMOS technology generation. However, electrostatic confinement and the transport behaviour in these devices are more complex, especially in or beyond the 5nm CMOS technology generation. At the heart of this thesis is the model-based research of aggressively-scaled NWTs suitable for implementation in or beyond the 5nm CMOS technology generation, including their physical and operational limitations and intrinsic parameter fluctuations. The Ensemble Monte Carlo approach with Poisson-Schrödinger (PS) quantum corrections was adopted for the purpose of predictive performance evaluation of NWTs. The ratio of the major to the minor ellipsoidal cross-section axis (cross-sectional aspect ratio - AR) has been identified as a significant contributing factor in device performance. Until now, semiconductor industry players have carried out experimental research on NWTs with two different cross-sections: circular cylinder (or elliptical) NWTs and nanosheet (or nanoslab) NWTs. Each version has its own benefits and drawbacks; however, the key difference between these two versions is the cross-sectional AR. Several critical design questions, including the optimal NWT cross-sectional aspect ratio, remain unanswered. To answer these questions, the AR of a GAA NWT has been investigated in detail in this research maintaining the cross-sectional area constant. Signatures of isotropic charge distributions within Si NWTs were observed, exhibiting the same attributes as the golden ratio (Phi), the significance of which is well-known in the fields of art and architecture. To address the gap in the existing literature, which largely explores NWT scaling using single-channel simulation, thorough simulations of multiple channels vertically-stacked NWTs have been carried out with different cross-sectional shapes and channel lengths. Contact resistance, non-equilibrium transport and quantum confinement effects have been taken into account during the simulations in order to realistically access performance and scalability. Finally, the individual and combined effects of key statistical variability (SV) sources on threshold voltage (VT), subthreshold slope (SS), ON-current (Ion) and drain-induced barrier lowering (DIBL) have been simulated and discussed. The results indicate that the variability of NWTs is impacted by device architecture and dimensions, with a significant reduction in SV found in NWTs with optimal aspect ratios. Furthermore, a reduction in the variability of the threshold voltage has been observed in vertically-stacked NWTs due to the cancelling-out of variability in double and triple lateral channel NWTs

Démonstration de l'intérêt des dispositifs multi-grilles auto-alignées pour les noeuds sub-10nm.

Les nombreuses modifications de la structure du transistor bulk ont permis de poursuivre la miniaturisation jusqu'à sa limite aux nœuds 32/28nm. Les technologies actuelles répondent au besoin d'un meilleur contrôle électrostatique en s'ouvrant vers l'industrialisation de transistors complètement dépletés, avec les architectures sur film mince (FDSOI) ou non planaires (TriGate FinFET bulk). Dans ce dernier cas, le substrat bulk reste limitant pour des applications à basse consommation. La combinaison de la technologie SOI et d'une architecture non-planaire conduit aux transistors TriGate sur SOI (ou TGSOI). Nous verrons l'intérêt de ces dispositifs et démontrerons qu'ils sont compatibles avec les techniques de contrainte. On montrera en particulier les améliorations de mobilité et de courants obtenus sur ces dispositifs de largeur inférieure à 15nm. Des simulations montrent également qu'un dispositif TGSOI peut être compatible avec les techniques de modulation de VT. Enfin, nous démontrons la possibilité de fabriquer des dispositifs ultimes à nanofils empilés avec une grille enrobante par une technique innovante de lithographie tridimensionnelle. La conception, la caractérisation physique et les premiers résultats électriques obtenus seront présentés. Ces solutions peuvent répondre aux besoins des nœuds sub-10nm.Changing the bulk transistor structure was sufficient so far to fulfill the scaling needs. The current technologies answer the needs of electrostatics control with the industrialization of fully depleted transistors, with thin-film (FDSOI) or non-planar (TriGate FinFet bulk) technologies. In the latter, bulk substrate is still an issue for low power applications. Combining SOI with multiple-gate structure gives rise to TriGate on SOI (or TGSOI). We will discuss the interest of such devices and will demonstrate their compatibility with strain techniques. We will focus on the mobility and current enhancement obtained on sub-15nm width devices. Simulations also demonstrate the compatibility of TGSOI with VT modulation technique. Finally, we demonstrate the fabrication through 3D lithography of ultimate stacked nanowires with a gate-all-around. The conception, physical characterization and first electrical results are presented.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF