8-Phase Ring oscillator for modern receivers

The evolution of receiver architectures, built in modern CMOS technologies, allows the design of high efficient receivers. A key block in modern receivers is the oscillator. The main objective of this thesis is to design a very low power and low area 8-Phase Ring Oscillator for biomedical applications (ISM and WMTS bands). Oscillators with multiphase outputs and variable duty cycles are required. In this thesis we are focused in 12.5% and 50% duty-cycles approaches. The proposed circuit uses eight inverters in a ring structure, in order to generate the output duty cycle of 50%. The duty cycle of 1/8 is achieved through the combination of the longer duty cycle signals in pairs, using, for this purpose, NAND gates. Since the general application are not only the wireless communications context, as well as industrial, scientific and medical plans, the 8-Phase Oscillator is simulated to be wideband between 100 MHz and 1 GHz, and be able to operate in the ISM bands (447 MHz-930 MHz) and WMTS (600 MHz). The circuit prototype is designed in UMC 130 nm CMOS technology. The maximum value of current drawn from a DC power source of 1.2 V, at a maximum frequency of 930 MHz achieved, is 17.54 mA. After completion of the oscillator layout studied (occupied area is 165 μm x 83 μm). Measurement results confirm the expected operating range from the simulations, and therefore, that the oscillator fulfil effectively the goals initially proposed in order to be used as Local Oscillator in RF Modern Receivers

A low power low voltage mixer for 2.4GHz applications in CMOS-90nm technology

Trabajo presentado al 13th DDECS celebrado en Viena del 14 al 16 de abril de 2010.This paper presents the design of a fully differential double balanced switched transconductor mixer for ZigBee applications in the 2.4GHz band. It provides programmable conversion gain by using an active load stage. The design includes RF and LO input matching networks. It has been implemented in a 90nm 1P9M CMOS process. Post-layout simulations show conversion gains of 12dB/20dB, NF of 18.9dB/18.1dB and power consumption of 4.1mW/4.4mW at high and low gain mode respectively from a 1.2V power supply. It also offers very good linearity performance.This work has been founded in part by the EC through the project SR2 - Short Range Radio (Catrene European project 2A105SR2 and Avanza I+D Spanish project TSI-020400-2008-71), the Spanish Government under project TEC2007-68072/MIC and the Spanish Regional Government of Junta de Andalucía under the project ACATEX (P09-TIC-5386).Peer Reviewe

Low-power/high-gain flexible complementary circuits based on printed organic electrochemical transistors

The ability to accurately extract low-amplitude voltage signals is crucial in several fields, ranging from single-use diagnostics and medical technology to robotics and the Internet of Things. The organic electrochemical transistor, which features large transconductance values at low operation voltages, is ideal for monitoring small signals. Its large transconductance translates small gate voltage variations into significant changes in the drain current. However, a current-to-voltage conversion is further needed to allow proper data acquisition and signal processing. Low power consumption, high amplification, and manufacturability on flexible and low-cost carriers are also crucial and highly anticipated for targeted applications. Here, we report low-power and high-gain flexible circuits based on printed complementary organic electrochemical transistors (OECTs). We leverage the low threshold voltage of both p-type and n-type enhancement-mode OECTs to develop complementary voltage amplifiers that can sense voltages as low as 100 $\mu$V, with gains of 30.4 dB and at a power consumption < 2.7 $\mu$W (single-stage amplifier). At the optimal operating conditions, the voltage gain normalized to power consumption reaches 169 dB/$\mu$W, which is > 50 times larger than state-of-the-art OECT-based amplifiers. In a two-stage configuration, the complementary voltage amplifiers reach a DC voltage gain of 193 V/V, which is the highest among emerging CMOS-like technologies operating at supply voltages below 1 volt. Our findings demonstrate that flexible complementary circuits based on printed OECTs define a power-efficient platform for sensing and amplifying low-amplitude voltage signals in several emerging beyond-silicon applications

Costas PLL Loop System for BPSK Detection

A 2GHz carrier recovery Costas Loop based BPSK detector is designed using CMOS 0.18μm technology. The designed BPSK detector consists of single to differential conversion circuit, phase/frequency detector, Voltage Controlled Oscillator, differential to single conversion circuit, first order loop filter and a third multiplier. Different architectures available for each block have been discussed along with the design methodology adopted. The schematics were simulated in analog design environment. The Costas loop presented in this work can sense both 0° and 180° phases at its input. Thus the Costas loop carrier recovery circuit overcomes the 180° phase ambiguity presented by the conventional PLL. The designed Costas loop for BPSK detection is able to detect and demodulate data rates up to 50Mbps. The loop can track with in the VCO frequency range of 1.99GHz to 2.01GHz. The lock range achieved for this loop is 20MHz. The power consumption of the Costas Loop BPSK detector was found to be 144mw

1.2V, 1.96mW @ 2.4GHz CMOS-90nm switched-transconductor mixer

This paper presents the design of a fully differential double balanced switched transconductor mixer for ZigBee applications in the 2.4GHz band. It provides programmable conversion gain by using an active load stage. The design includes RF and LO input matching networks. It has been implemented in a 90nm 1P9M CMOS process. Post-layout simulations show conversion gains of 12dB/20dB, NF of 18.9dB/18.1dB and power consumption of 4.1mW/4.4mW at high and low gain mode respectively from a 1.2V power supply. It also offers very good linearity performance.España, Gobierno TEC2007- 68072 / MICEspaña, Junta de Andalucía ACATEX (P09-TIC-5386

Design of an Active Harmonic Rejection N-Path Filter for Highly Tunable RF Channel Selection

As the number of wireless devices in the world increases, so does the demand for flexible radio receiver architectures capable of operating over a wide range of frequencies and communication protocols. The resonance-based channel-select filters used in traditional radio architectures have a fixed frequency response, making them poorly suited for such a receiver. The N-path filter is based on 1960s technology that has received renewed interest in recent years for its application as a linear high Q filter at radio frequencies. N-path filters use passive mixers to apply a frequency transformation to a baseband low-pass filter in order to achieve a high-Q band-pass response at high frequencies. The clock frequency determines the center frequency of the band-pass filter, which makes the filter highly tunable over a broad frequency range. Issues with harmonic transfer and poor attenuation limit the feasibility of using N-path filters in practice. The goal of this thesis is to design an integrated active N-path filter that improves upon the passive N-path filter’s poor harmonic rejection and limited outof- band attenuation. The integrated circuit (IC) is implemented using the CMRF8SF 130nm CMOS process. The design uses a multi-phase clock generation circuit to implement a harmonic rejection mixer in order to suppress the 3rd and 5th harmonic. The completed active N-path filter has a tuning range of 200MHz to 1GHz and the out-ofband attenuation exceeds 60dB throughout this range. The frequency response exhibits a 14.7dB gain at the center frequency and a -3dB bandwidth of 6.8MHz

Single-chip inverter for active filters

Generally inverter-based active filters, which employ pulse-width-modulated (PWM) techniques, use microprocessors for overall control and discrete logic for the generation of switching patterns. Because of the complexity of control required, discrete logic circuits tend to have a very high component count, making system design inflexible, expensive and less reliable than integrated circuit implementation. The work reported here presents a novel design of a single-chip controlled PWM inverter-based active filter, which addresses these issues

Design of a 14-bit fully differential discrete time delta-sigma modulator

Analog to digital converters play an essential role in modern mixed signal circuit design. Conventional Nyquist-rate converters require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can be implemented using simple and high-tolerance analog components. Moreover, sampling at high frequency eliminates the need for abrupt cutoffs in the analog anti-aliasing filters. A noise shaping technique is also used in DS converters in addition to oversampling to achieve a high resolution conversion. A significant advantage of the method is that analog signals are converted using simple and high-tolerance analog circuits, usually a 1-bit comparator, and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter. In this thesis, a technique to design the discrete time DS converters for 25 kHz baseband signal bandwidth will be described. The noise shaping is achieved using a switched capacitor low-pass integrator around the 1-bit quantizer loop. A latched-type comparator is used as the quantizer of the DS converter. A second order DS modulator is implemented in a TSMC 0.35 µm CMOS technology using a 3.3 V power supply. The peak signal-to-noise ratio (SNR) simulated is 87 dB; the SNDR simulated is 82 dB which corresponds to a resolution of 14 bits. The total static power dissipation is 6.6 mW

CMOS Gate Drive IC With Embedded Cross Talk Suppression Circuitry For Power Electronic Applications

Electric Vehicle (EV) propulsion systems are typically driven by three phase-leg motor drives, which consist of a pair of power devices. Each one of these power devices must be driven by a gate driver chip to operate efficiently. The proposed gate driver solution considers driving SiC devices and has been developed to increase the efficiency of such devices, which requires new gate driver solutions that can properly handle the high switching speeds of these devices. The higher switching speeds seen in SiC devices have brought forth a new problem: cross-talk. Cross-talk can be seen in the false switching of the partner device of a phase-leg as the driven device is being switched. Therefore, crosstalk suppression circuitry must be considered when developing a new gate driver solution. The proposed gate driver includes embedded cross talk suppression. The new gate driver topology will be presented and will show the cross talk suppression operation