Evaluation and implementation of a 5-level hybrid DC-DC converter

In this work, a hybrid voltage regulator topology is analyzed, implemented, and evaluated. The common topologies of DC-DC converters have proven to be lacking in some aspects, such as integrability for buck converters, or maximum efficiency for switched-capacitor regulators. The hybrid topology tackles these shortcomings by combining the advantages of switched-capacitor and inductor-based voltage regulators. A 5-level buck converter is evaluated, implemented, and compared to other converter implementations using the same components. The 5-Level Buck converter can achieve 5 different levels, allowing it to cover 4 operation regions, each between 2 levels. Accordingly, it covers a wide range of output voltages. By reducing the voltage difference at the inductor input, the 5-level buck converter can use smaller inductor compared to both 3-level and conventional buck converters which makes it cheaper, smaller in size, and much more efficient. Simulations show proper functionality of the 5-Level topology, while putting restrictions on the inductor size, efficiency, and component footprint (or total converter area). A test PCB is implemented for verification of the functionality and experimental measurements show that for the same switching frequency and inductor size, the 5-level buck converter achieves up to 15% efficiency improvement over a conventional buck converter and a 3-level buck converter at certain output voltage ranges. Peak efficiency of 94% has been achieved by the 5-Level hybrid converter, which includes all external switching and conduction losses. The proposed hybrid topology proved to yield high conversion efficiency even in the face of component size limitations, which indicates potential benefit in using multilevel converters for several off-chip as well as on-chip applications

Design Space Evaluation for Resonant and Hard-charged Switched Capacitor Converters

USB Power Delivery enables a fixed ratio converter to operate over a wider range of output voltages by varying the input voltage. Of the DC/DC step-down converters powered from this type of USB, the hard-charged Switched Capacitor circuit is of interest to industry for its potential high power density. However implementation can be limited by circuit efficiency. In fully resonant mode, the efficiency can be improved while also enabling current regulation. This expands the possible applications into battery chargers and eliminates the need for a two-stage converter.In this work, the trade-off in power loss and area between the hard-charged and fully resonant switched capacitor circuit is explored using a technique that remains agnostic to inductor technology. The loss model for each converter is presented as well as discussion on the restrained design space due to parasitics in the passive components. The results are validated experimentally using GaN-based prototype converters and the respective design spaces are analyzed

Integrated Voltage Regulators with Thin-Film Magnetic Power Inductors

Integration of alternative materials and devices with CMOS will expand functionality and improve performance of established applications in the era of diminishing returns from Moore's Law scaling. In particular, integration of thin-film magnetic materials will enable improvements in energy efficiency of digital computing applications by enabling integrated power conversion and management with on-chip power inductors. Integrated voltage reg- ulators will also enable fine-grained power management, by providing dynamic scaling of the supply voltage in concert with the clock frequency of synchronous logic to throttle power consumption at periods of low computational demand. Implementation of integrated power conversion requires high capacity energy storage devices. This is best achieved with integration of thin-film magnetic materials for high quality on-chip power inductors. This thesis describes a body of work conducted to develop integrated switch-mode voltage regulators with thin-film magnetic power inductors. Soft-magnetic materials and inductor topologies are selected and optimized, with intent to maximize efficiency and current density of the integrated regulators. Custom integrated circuits are designed and fabricated in 45nm-SOI to provide the control system and power-train necessary to drive the power inductors. A silicon interposer is designed and fabricated in collaboration with IBM Research to integrate custom power inductors by 2.5D chip stacking, enabling power conversion with current density greater than 10A/mm2. The concepts and designs developed from this work will enable significant improvements in performance-per-watt of future microprocessors

Design Techniques of Highly Integrated Hybrid-Switched-Capacitor-Resonant Power Converters for LED Lighting Applications

The Light-emitting diodes (LEDs) are rapidly emerging as the dominant light source given their high luminous efficacy, long lift span, and thanks to the newly enacted efficiency standards in favor of the more environmentally-friendly LED technology. The LED lighting market is expected to reach USD 105.66 billion by 2025. As such, the lighting industry requires LED drivers, which essentially are power converters, with high efficiency, wide input/output range, low cost, small form factor, and great performance in power factor, and luminance flicker. These requirements raise new challenges beyond the traditional power converter topologies. On the other hand, the development and improvement of new device technologies such as printed thin-film capacitors and integrated high voltage/power devices opens up many new opportunities for mitigating such challenges using innovative circuit design techniques and solutions. Almost all electric products needs certain power delivery, regulation or conversion circuits to meet the optimized operation conditions. Designing a high performance power converter is a real challenge given the market’s increasing requirements on energy efficiency, size, cost, form factor, EMI performance, human health impact, and so on. The design of a LED driver system covers from high voltage AC/DC and DC/DC power converters, to high frequency low voltage digital controllers, to power factor correction (PFC) and EMI filtering techniques, and to safety solutions such as galvanic isolation. In this thesis, we study design challenges and present corresponding solutions to realize highly integrated and high performance LED drivers combining switched-capacitor and resonant converters, applying re-configurable multi-level circuit topology, utilizing sigma delta modulation, and exploring capacitive galvanic isolation. A hybrid switched-capacitor-resonant (HSCR) LED driver based on a stackable switched-capacitor (SC) converter IC rated for 15 to 20 W applications. Bulky transformers have been replaced with a SC ladder to perform high-efficiency voltage step-down conversion; an L-C resonant output network provides almost lossless current regulation and demonstrates the potential of capacitive galvanic isolation. The integrated SC modules can be stacked in the voltage domain to handle a large range of input voltage ranges that largely exceed the voltage limitation of the medium-voltage-rated 120 V silicon technology. The LED driver demonstrates > 91% efficiency over a rectified input DC voltage range from 160 VDC to 180 VDC with two stacked ICs; using a stack of four ICs > 89.6% efficiency is demonstrated over an input range from 320 VDC to 360 VDC . The LED driver can dim its output power to around 10% of the rated power while maintaining >70% efficiency with a PWM controlled clock gating circuit. Next, the design of AC main rectifier and inverter front end with sigma delta modulation is described. The proposed circuits features a pair of sigma delta controlled multilevel converters. The first is a multilevel rectifier responsible for PFC and dimming. The second is a bidirectional multilevel inverter used to cancel AC power ripple from the DC bus. The system also contains an output stage that powers the LEDs with DC and provides for galvanic isolation. Its functional performance indicates that integrated multilevel converters are a viable topology for lighting and other similar applications

MODELING AND CONTROL OF DIRECT-CONVERSION HYBRID SWITCHED-CAPACITOR DC-DC CONVERTERS

Efficient power delivery is increasingly important in modern computing, communications, consumer and other electronic systems, due to the high power demand and thermal concerns accompanied by performance advancements and tight packaging. In pursuit of high efficiency, small physical volume, and flexible regulation, hybrid switched-capacitor topologies have emerged as promising candidates for such applications. By incorporating both capacitors and inductors as energy storage elements, hybrid topologies achieve high power density while still maintaining soft charging and efficient regulation characteristics. However, challenges exist in the hybrid approach. In terms of reliability, each flying capacitor should be maintained at a nominal `balanced\u27 voltage for robust operation (especially during transients and startup), complicating the control system design. In terms of implementation, switching devices in hybrid converters often need complex gate driving circuits which add cost, area, and power consumption. This dissertation explores techniques that help to mitigate the aforementioned challenges. A discrete-time state space model is derived by treating the hybrid converter as two subsystems, the switched-capacitor stage and the output filter stage. This model is then used to design an estimator that extracts all flying capacitor voltages from the measurement of a single node. The controllability and observability of the switched-capacitor stage reveal the fundamental cause of imbalance at certain conversion ratios. A new switching sequence, the modified phase-shifted pulse width modulation, is developed to enable natural balance in originally imbalanced scenarios. Based on the model, a novel control algorithm, constant switch stress control, is proposed to achieve both output voltage regulation and active balance with fast dynamics. Finally, the design technique and test result of an integrated hybrid switched-capacitor converter are reported. A proposed gate driving strategy eliminates the need for external driving supplies and reduces the bootstrap capacitor area. On-chip mixed signal control ensures fast balancing dynamics and makes hard startup tolerable. This prototype achieves 96.9\% peak efficiency at 5V:1.2V conversion and a startup time of 12$\mu s$, which is over 100 times faster than the closest prior art. With the modeling, control, and design techniques introduced in this dissertation, the application of hybrid switched-capacitor converters may be extended to scenarios that were previously challenging for them, allowing enhanced performance compared to using traditional topologies. For problems that may require future attention, this dissertation also points to possible directions for further improvements

Power delivery mechanisms for asynchronous loads in energy harvesting systems

PhD ThesisFor systems depending on methods, a fundamental contradiction in the power delivery chain has existed between conventional to supply it. DC/DC conversion (e.g.) has therefore been an integral part of such systems to resolve this contradiction. be made tolerant to a much wider range of Vdd variance. This may open up opportunities for much more energy efficient methods of power delivery. performance of different power delivery mechanisms driving both asynchronous and synchronous loads directly from a harvester source bypassing bulky energy method, which employs a energy from a EH circuit depending on load and source conditions, is developed. through comprehensive comparative analysis. Based on the novel CBB power delivery method, an asynchronous controller is circuits to work with tasks. The successful asynchronous control design drives a case study that is meant to explore relations between power path and task path. To deal with different tasks with variable harvested power, systems may have a range of operation conditions and thus dynamically call for CBB or SCC type power set of capacitors to form CBB or SCC is implemented with economic system size. This work presents an unconventional way of designing a compact-size, quick- circuit overcome large voltage variation in EH systems and implement smart power management for harsh EH environment. The power delivery mechanisms (SCC, employed to help asynchronous- logic-based chip testing and micro-scale EH system demonstrations

Toward high-efficiency high power density single-phase DC-AC and AC-DC power conversion - architecture, topology and control

Power conversion between the single-phase AC grid and DC sources or loads plays an indispensable role in modern electrical energy system for both generation and consumption. The renewable resources and electrical energy storage are integrated to the grid through inverters. Telecoms, data centers and the rest of the digital world is powered by the grid through rectifiers. Existing and emerging applications all demand the DC-AC and AC-DC systems to be not only more efficient to reduce energy consumption, but also more compact to reduce cost and improve portability. Therefore, new AC-DC and DC-AC converter designs that improve the efficiency and power density of the system is a critical area of research and is the focus of this dissertation. The recent development of wide band-gap devices stimulates a new round of improvement on efficiency and power density of AC-DC converters. However, despite the new transistors used, the fundamental system architecture and topology remain relatively unchanged, which is becoming the bottleneck for further improvement. This dissertation explores new architecture, topology and control to overcome this bottleneck, targeting an order-of-magnitude improvement on power density and comparable efficiency to the conventional design. The proposed solutions build on two key innovations: the series-stacked buffer architecture for twice-line-frequency power pulsation decoupling in single-phase AC-DC and DC-AC conversion, and the flying capacitor multilevel topology for power transfer and waveform conversion between AC and DC. This work provides complete solutions for these ideas, including the theoretical development, design procedure, control method, hardware implementation and experimental characterization

Image compression and energy harvesting for energy constrained sensors

Title from PDF of title page, viewed on June 21, 2013Dissertation advisor: Walter D. Leon-SalasVitaIncludes bibliographic references (pages 176-[187])Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2013The advances in complementary metal-oxide-semiconductor (CMOS) technology have led to the integration of all components of electronic system into a single integrated circuit. Ultra-low power circuit techniques have reduced the power consumption of circuits. Moreover, solar cells with improved efficiency can be integrated on chip to harvest energy from sunlight. As a result of all the above, a new class of miniaturized electronic systems known as self-powered system on a chip has emerged. There is an increasing research interest in the area of self-powered devices which provide cost-effective solutions especially when these devices are used in the areas that changing or replacing batteries is too costly. Therefore, image compression and energy harvesting are studied in this dissertation. The integration of energy harvesting, image compression, and an image sensor on the same chip provides the energy source to charge a battery, reduces the data rate, and improves the performance of wireless image sensors. Integrated circuits of image compression, solar energy harvesting, and image sensors are studied, designed, and analyzed in this work. In this dissertation, a hybrid image sensor that can perform the tasks of sensing and energy harvesting is presented. Photodiodes of hybrid image sensor can be programmed as image sensors or energy harvesting cells. The hybrid image sensor can harvest energy in between frames, in sleep mode, and even when it is taking images. When sensing images and harvesting energy are both needed at the same time, some pixels have to work as sensing pixels, and the others have to work as solar cells. Since some pixels are devoted to harvest energy, the resolution of the image will be reduced. To preserve the resolution or to keep the fair resolution when a lot of energy collection is needed, image reconstruction algorithms and compressive sensing theory provide solutions to achieve a good image quality. On the other hand, when the battery has enough charge, image compression comes into the picture. Multiresolution decomposition image compression provides a way to compress image data in order to reduce the energy need from data transmission. The solution provided in this dissertation not only harvests energy but also saves energy resulting long lasting wireless sensors. The problem was first studied at the system level to identify the best system-level configuration which was then implemented on silicon. As a proof of concept, a 32 x 32 array of hybrid image sensor, a 32 x 32 array of image sensor with multiresolution decomposition compression, and a compressive sensing converter have been designed and fabricated in a standard 0.5 [micrometer] CMOS process. Printed circuit broads also have been designed to test and verify the proposed and fabricated chips. VHDL and Matlab codes were written to generate the proper signals to control, and read out data from chips. Image processing and recovery were carried out in Matlab. DC-DC converters were designed to boost the inherently low voltage output of the photodiodes. The DC-DC converter has also been improved to increase the efficiency of power transformation.Introduction -- Hybrid imager system and circuit design -- Hybrid imager energy harvesting and image acquisition results and discussion -- Detailed description and mathematical analysis for a circuit of energy harvesting using on-chip solar cells -- Multiresolution decomposition for lossless and near-lossless compression -- An incremental [sigma-delta] converter for compressive sensing -- Detailed description of a sigma-delta random demodulator converter architecture for compressive sensing applications -- Conclusion -- Appendix A. Chip pin-out -- Appendix B. Schematics -- Appendix C. Pictures of custom PC

High-performance power converters leveraging capacitor-based energy transfer

The increasing demand for high performance power conversion systems continuously pushes for improvement in efficiency and power density. This dissertation focuses on a topological effort to efficiently utilize the active and passive devices. In particular, a hybrid approach is adopted, where both capacitors and inductors are used in the voltage conversion and power transfer process. Conventional capacitor-based converters, called switched-capacitor (SC) converters, suffer from poor efficiency due to the inevitable charge redistribution process. With a strategic placement of one or more inductors, the charge redistribution loss can be eliminated by inductively charging/discharging the capacitors, a process called soft-charging operation. As a result, the capacitor size can be greatly reduced without reducing the efficiency. A general analytical framework is presented, which determines whether an arbitrary SC topology is able to achieve full soft-charging operation with a single inductor. For topologies that cannot, a split-phase control technique is introduced, which amends existing two-phase controls to completely eliminate the charge redistribution loss. In addition, alternative placements of inductors are explored to extend the family of hybrid converters. The hybrid converters can have two modes of operation, the fixed-ratio mode and pulse width modulated (PWM) mode. The fixed-conversion-ratio hybrid converters operate in a similar manner to that of a conventional SC converter, with the addition of a soft-charging inductor. The switching frequency of such converters can be adjusted to operate in either zero current switching (ZCS) mode or continuous conduction mode (CCM), which allows for the trade-off of switching loss and conduction loss. It is shown that the capacitor and inductor values can be selected to achieve a minimal passive component volume, which can be significantly smaller than that of a conventional SC converter or a magnetic-based converter. On the other hand, PWM-based hybrid converters generate a PWM rectangular wave as the terminal voltage to the inductor, similar to the operation of a buck converter. In contrast to conventional SC converters, such hybrid converters can achieve lossless and continuous regulation of the output voltage. Compared to buck converters, the required inductor is greatly reduced, as well as the switch stress. A 80 - 170 V input, 12 - 24 V output prototype PWM Dickson converter is implemented using GaN switches. The measured peak efficiency is 97%, and high efficiency can be maintained over the entire input and output operating range. In addition, the similarity between multilevel converters (for example, flying capacitor multilevel (FCML) converters) and the PWM-based hybrid SC converters is discussed. Both types of converters can be seen as a hybrid converter which uses both capacitors and inductors for energy transfer. A general framework to compare these converters, along with conventional buck converters, is proposed. In this framework, the power losses (including conduction loss and switching loss) are kept constant, while the total passive component volume is used as the figure of merit. Based on the principle of maximizing energy utilization of passive components, a 7-level FCML converter and an active energy buffer are designed and implemented for single phase dc-ac applications. In addition, the stand-alone system includes a start-up circuitry, EMC filter and auxiliary power supply. The enclosed box achieves a combined power density of 216 W/in^3 and an efficiency of 97.4%, and compares favorably against the state-of-the-art designs under the same specification. To further improve the efficiency and power density, soft-switching techniques are investigated and applied on the hybrid converters. A zero voltage switching (ZVS) technique is introduced for both the fixed-ratio mode and the PWM mode operated hybrid converters. The previous hardware prototypes are modified for ZVS operation, and prove the feasibility of simultaneous soft-charging and soft-switching operation. Last but not the least, some of the practical issues associated with the hybrid converter are discussed, such as practical capacitor selection, capacitor voltage balancing and other circuit implementation challenges. Future work based on these topics is given. In summary, these hybrid converters are suited for applications where extreme efficiency and power density are critical. Through efficient utilization of active and passive devices, the hybrid topologies can offer a greater optimization opportunity and ability to take advantage of technology improvement than is possible with conventional designs