Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Phasemeter core for intersatellite laser heterodyne interferometry: modelling, simulations and experiments

Inter satellite laser interferometry is a central component of future space-borne gravity instruments like LISA, eLISA, NGO and future geodesy missions. The inherently small laser wavelength allows to measure distance variations with extremely high precision by interfering a reference beam with a measurement beam. The readout of such interferometers is often based on tracking phasemeters, able to measure the phase of an incoming beatnote with high precision over a wide range of frequencies. The implementation of such phasemeters is based on all digital phase-locked loops, hosted in FPGAs. Here we present a precise model of an all digital phase locked loop that allows to design such a readout algorithm and we support our analysis by numerical performance measurements and experiments with analog signals.Comment: 17 pages, 6 figures, accepted for publication in CQ

Design and layout strategies for integrated frequency synthesizers with high spectral purity

Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.BMBF, 03ZZ0512A, Zwanzig20 - Verbundvorhaben: fast-spot; TP1: Modularer Basisband- Prozessor mit extrem hohen Datenraten, sehr kurzen Latenzzeiten und SiGe-Analog-Frontend-IC-Fertigung bei >200 GHz Trägerfrequen

Performance analysis of 1ϕ T/4 PLLs with secondary control path in current sensorless bridgeless PFCs

New power factor correction (PFC) stages such as bridgeless converters and the associated current shaping techniques require grid synchronization to ensure unity Displacement Power Factor (DPF). Sensorless line current rebuilding algorithms also need synchronization with the line voltage to compensate at least for part of the current estimation error. The application of a secondary control path to reach faster and more robustly the proper operation point previously applied in single/three-phase PLLs in grid connected converters is here proposed for the current sensorless bridgeless PFCs. This work analyzes the performance of three single-phase T/4 PLL structures, first without secondary control path, and later with feedforward and feedback secondary control paths, both in simulation and experimentally, and evaluates their applicability to current sensorless digitally controlled single phase bridgeless PFCs based on the current rebuilding technique.This work has been supported by the Spanish Ministry of Economy and Competitiveness under grant TEC2014-52316-R ECOTREND Estimation and Optimal Control for Energy Conversion with Digital Devices

Impact and modeling of phase noise in mmW beamforming systems

Abstract. Due to the exponential growth of wireless communication, mobile communication applications require more bandwidth available in higher operating frequencies. High centre frequency makes the systems sensitive for phase variations caused by the phase noise (PN) of the imperfect local oscillators (LOs) used in wireless transceivers. Moreover, wide bandwidth also makes the faster phase variations of the phase noise spectra have an impact on the overall system performance by reducing effective signal-to-noise-ratio. These fast variations seen in the high offset frequencies in the phase noise spectra are typically ignored in the communication systems because the traditional system bandwidths are in order of megahertz, or in maximum few gigahertz. In mmW frequencies, i.e., at 30–300 GHz, the transceivers are typically using multiple antenna elements to achieve the required link range by highly directional beams. Often so-called phased arrays are used to implement the multi-antenna transceiver, where the beamforming is mostly performed in the analog domain by digitally controllable mmW phase shifters. For generating multiple beams from the same transceivers, more than one phased array is typically used in the same platform. The phased arrays often share a single LO, for multiple antenna elements. A typical LO generation architecture is containing a base clock, phased-locked loop (PLL), and some frequency multipliers to achieve the target mmW operating frequency. In multi-array systems, the LO signal can be divided into phased arrays in multiple domains, i.e., the arrays can have an independent clock, and a shared clock, but independent PLLs, shared PLL, or even the final mmW LO can be shared. In different architectures, the phase noise has different behavior, and it can have an impact for example on the beamforming accuracy. This thesis focuses on the effects of phase noise on milimeter-wave (mmW) beamforming systems to study different LO routing architectures. We mainly focus on LO architecture with multiple phased arrays that intend to make a common beamformer and their impact on overall system-level phase noise performance. The specific focus is given to the behavior of the wideband phase noise. The phase noise is modeled by using baseband equivalent models where a gaussian phase noise source is filtered by a filter modeling the equivalent phase noise spectra. The parameterization of the model is based on commercial LO phase noise spectra. The behavior is studied in different LO schemes in single-beam and multi-beam scenarios by using simple examples. The simulations are mostly carried out by using continuous-wave signals, but also the single-carrier modulated QAM waveform is demonstrated. The simulations are performed in MATLAB

Control law synthesis for distributed multi-agent systems: Application to active clock distribution networks

International audienceIn this paper, the problem of active clock distribution network synchronization is considered. The network is made of identical oscillators interconnected through a distributed array of phase-locked-loops (PLLs). The problem of the PLL network design is reformulated, from a control theory point of view, as a control law design for a distributed multi-agent system. Inspired by the decentralized control law design methodology using the dissipativity input-output approach, the particular topology of interconnected subsystems is exploited to solve the problem by applying a convex optimization approach involving simple Linear Matrix Inequality (LMI) constraints. After choosing the dissipativity properties which is satisfied by the interconnection matrix, the constraints are transformed into an H ∞ norm constraint on a particular transfer function that must be fulfilled for global stability. Additional constraints on inputs and outputs are introduced in order to ensure the desired performance specifications during the H ∞ control design procedure

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

Noise Weighting in the Design of {\Delta}{\Sigma} Modulators (with a Psychoacoustic Coder as an Example)

A design flow for {\Delta}{\Sigma} modulators is illustrated, allowing quantization noise to be shaped according to an arbitrary weighting profile. Being based on FIR NTFs, possibly with high order, the flow is best suited for digital architectures. The work builds on a recent proposal where the modulator is matched to the reconstruction filter, showing that this type of optimization can benefit a wide range of applications where noise (including in-band noise) is known to have a different impact at different frequencies. The design of a multiband modulator, a modulator avoiding DC noise, and an audio modulator capable of distributing quantization artifacts according to a psychoacoustic model are discussed as examples. A software toolbox is provided as a general design aid and to replicate the proposed results.Comment: 5 pages, 18 figures, journal. Code accompanying the paper is available at http://pydsm.googlecode.co