On Combinational Networks with Restricted Fan-Out

Fan-out-free networks of AND, OR, NOT, EXOR, and MAJORITY gates are considered. Boolean functions for which such networks exist are defined to be fan-out free. The paper solves the following problems regarding the fan-out-free networks and functions. 1) Characterization of the class of fan-out-free functions: The characterization given is constructive in the sense that if a given function is fan-out free one obtains a fan-out-free network to realize it. 2) Counting the class of fan-out-free functions: After establishing a correspondence between a fan-out-free function and a normalized network realizing it, a series of formulas are developed to count distinct normal networks for any subset of the five gates mentioned above. 3) Fault Diagnosis: Methods are developed to detect multiple faults and to locate single faults in arbitrary fan-out-free networks

Fault detection in asynchronous sequential circuits

As the asynchronous sequential circuit has become more and more important to digital systems in recent years high reliability and simple maintenance of the circuit is stressed. This paper presents a fault-detection algorithm which will be applicable to most of the practical asynchronous sequential circuits. The asynchronous sequential circuit is treated from the combinatoric point of view. First the minimal set of states, both stable states and unstable states, sufficient to detect all possible faults of the circuit is found from the fault table. Then a test sequence is generated to go through these states. It is assumed that testing outputs can be added. Simple and systematic techniques are also presented for the construction of fault table and the generation of test sequence. The usefulness of this algorithm increases as the density of the stable states associated with the circuit increases --Abstract, page ii

Study of diagnosability of binary address decoders

This paper studies the diagnosability of various types of binary address decoders. An attempt is made to develop a theory of diagnosis for logical faults that might occur in these logic nets. The developed theory is used to analyze these logic nets for various input combinations. Finally, the derivation of optimum diagnostic test sequences is considered --Abstract, Page i

Techniques for the realization of ultra- reliable spaceborne computer Final report

Bibliography and new techniques for use of error correction and redundancy to improve reliability of spaceborne computer

Fault detection on sequential machines

This paper presents an algorithm for deriving an optimum test sequence for detecting faults in a synchronous machine. In this study, the flow table is used as a tool to generate the fault detection tests. The fault stuck-at-1 (or stuck-at-0 ) is said to be present when a permanent signal valued 1 (or 0) appears on a component of the machine. Only single faults are treated . The result of the procedure is one or more test sequences guaranteed to detect a set of faults (Fp). First, sequential machines with feedback lines as memory elements are considered . Then the memory elements are changed to R-S flip-flops. Finally, several suggestions for further work are made --Abstract, Page ii

A survey of an introduction to fault diagnosis algorithms

This report surveys the field of diagnosis and introduces some of the key algorithms and heuristics currently in use. Fault diagnosis is an important and a rapidly growing discipline. This is important in the design of self-repairable computers because the present diagnosis resolution of its fault-tolerant computer is limited to a functional unit or processor. Better resolution is necessary before failed units can become partially reuseable. The approach that holds the greatest promise is that of resident microdiagnostics; however, that presupposes a microprogrammable architecture for the computer being self-diagnosed. The presentation is tutorial and contains examples. An extensive bibliography of some 220 entries is included

Fault Testing for Reversible Circuits

Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation. We consider the test set generation problem. Reversibility affects the testing problem in fundamental ways, making it significantly simpler than for the irreversible case. For example, we show that any test set that detects all single stuck-at faults in a reversible circuit also detects all multiple stuck-at faults. We present efficient test set constructions for the standard stuck-at fault model as well as the usually intractable cell-fault model. We also give a practical test set generation algorithm, based on an integer linear programming formulation, that yields test sets approximately half the size of those produced by conventional ATPG.Comment: 30 pages, 8 figures. to appear in IEEE Trans. on CA