Modeling and Design Techniques for 3-D ICs under Process, Voltage, and Temperature Variations

Three-dimensional (3-D) integration is a promising solution to further enhance the density and performance of modern integrated circuits (ICs). In 3-D ICs, multiple dies (tiers or planes) are vertically stacked. These dies can be designed and fabricated separately. In addition, these dies can be fabricated in different technologies. The effect of different sources of variations on 3-D circuits, consequently, differ from 2-D ICs. As technology scales, these variations significantly affect the performance of circuits. Therefore, it is increasingly important to accurately and efficiently model different sources of variations in 3-D ICs. The process, voltage, and temperature variations in 3-D ICs are investigated in this dissertation. Related modeling and design techniques are proposed to design a robust 3-D IC. Process variations in 3-D ICs are first analyzed. The effect of process variations on synchronization and 3-D clock distribution networks, is carefully studied. A novel statistical model is proposed to describe the timing variation in 3-D clock distribution networks caused by process variations. Based on this model, different topologies of 3-D clock distribution networks are compared in terms of skew variation. A set of guidelines is proposed to design 3-D clock distribution networks with low clock uncertainty. Voltage variations are described by power supply noise. Power supply noise in 3-D ICs is investigated considering different characteristics of potential 3-D power grids in this thesis. A new algorithm is developed to fast analyze the steady-state IR-drop in 3-D power grids. The first droop of power supply noise, also called resonant supply noise, is usually the deepest voltage drop in power distribution networks. The effect of resonant supply noise on 3-D clock distribution networks is investigated. The combined effect of process variations and power supply noise is modeled by skitter consisting of both skew and jitter. A novel statistical model of skitter is proposed. Based on this proposed model and simulation results, a set of guidelines has been proposed to mitigate the negative effect of process and voltage variations on 3-D clock distribution networks. Thermal issues in 3-D ICs are considered by carefully modeling thermal through silicon vias (TTSVs) in this dissertation. TTSVs are vertical vias which do not carry signals, dedicated to facilitate the propagation of heat to reduce the temperature of 3-D ICs. Two analytic models are proposed to describe the heat transfer in 3-D circuits related to TTSVs herein, providing proper closed-form expressions for the thermal resistance of the TTSVs. The effect of different physical and geometric parameters of TTSVs on the temperature of 3-D ICs is analyzed. The proposed models can be used to fast and accurately estimate the temperature to avoid the overuse of TTSVs occupying a large portion of area. A set of models and design techniques is proposed in this dissertation to describe and mitigate the deleterious effects of process, voltage, and temperature variations in 3-D ICs. Due to the continuous shrink in the feature size of transistors, the large number of devices within one circuit, and the high operating frequency, the effect of these variations on the performance of 3-D ICs becomes increasingly significant. Accurately and efficiently estimating and controlling these variations are, consequently, critical tasks for the design of 3-D ICs

Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

Extreme temperature memory design with the reduced design time using silicon on sapphire technology

This dissertation describes high temperature memories as part of the design for 275 degrees C HC11 microcontroller and 200 degrees C LEON3 processor using the 0.5um Peregrine SOS CMOS technology. The memories having been designed include: a 4K on-chip SRAM, 512byte on-chip ROM, 4K SPI-SRAM, 2K SPI-ROM , 2K x16 off-chip SRAM, 128 x 32 cache , 32 x 32 cache, and SRAM design with Encounter support. The 4K SPI-SRAM testing and 2K SPI-ROM confirmed operations across room to 275 degrees C. The LEON3 testing confirmed operations across room to 200 degrees C including 128 x 32 cache and 32 x 32 cache. With testing analysis, good candidates for error sources of memory failure were found and memory yield can be improved for future memory designs. The error sources are believed to be mainly the silicon defects and/or strong (leaky NMOS) transistors, and Metal2 shorts. The developed methodologies presented are essential for the microprocessor and memory designs across process and temperature corners. Data for ION and IOFF, threshold and mobility was developed with temperature. High temperature 3.3V cell libraries were developed for the LEON3 and HC11. The memories were designed with aid from the measured data, addressing write and read stability in the context of floating body effect, kink effect, shrinking ION/IOFF currents. Especially a novel 6T PMOS SRAM cell and a stacked-NMOS sense amp were designed to solve these issues. The LEON3/HC11 was placed and routed with the standard cell library and characterized memories. Finally, SRAM design with Encounter support has been demonstrated to be a fast time to market memory design solution

Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications

Ring-based resonant standing wave oscillators have been shown to be a useful clocking tech-nique that can distribute and generate a high frequency, low skew, low power, and stable clock signal. By using through-silicon-vias, this type of standing wave oscillator can be used to gener-ate the clocking scheme for 3D integrated circuits. In this thesis, we propose the use of such 3D standing wave oscillators and show how independent 3D oscillators in different stacks can syn-chronize through the use of a redistribution layer stub. Inter-chip clock synchronization is then accomplished without the need for a PLL. In addition, we propose the first 3D ring-based resonant standing wave oscillator bootstrap and reset circuit to initialize and stop oscillation. Using a 3D ring-based resonant standing wave oscillator, we propose a ring-based data fabric for 3D stacked DRAM and compare the results with existing approaches such as High Bandwidth Memory (HBM) or Wide I/O memory. We show that our Memory Architecture using a Ring-based Scheme (MARS) can provide the increases in speed necessary to overcome current memory bottlenecks, and can scale effectively as future 3D stacks become larger. Our MARS can trade off power, throughput, and latency to match different application requirements. By using a narrow bus, and connecting it to all channels, the MARS8 can provide an alternative memory configuration with ∼ 6.9× lower power consumption than HBM, and ∼ 2.7× faster speeds than Wide I/O. Using multiple ring topologies in the same stack, the channel count can double from 8 to 16, and then to 32. This is possible since MARS uses about 4× fewer TSVs per channel than HBM or Wide I/O. This provides speeds up to ∼ 4.2× faster than traditional HBM. This scalable architecture allows higher throughput and faster system performance for next-generation DRAM. The MARS topology proposed in this thesis can be used in a variety of computing systems, from lightweight IoT to large-scale data centers

Bringing NoCs to 65nm

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of Noc-Based interconnect design in nanometer CMOS. The author present experimental results from fully working 65-NM Noc Designs and a detailed scalability analysis

A parallel algorithm for switch-level timing simulation on a hypercube multiprocessor

The parallel approach to speeding up simulation is studied, specifically the simulation of digital LSI MOS circuitry on the Intel iPSC/2 hypercube. The simulation algorithm is based on RSIM, an event driven switch-level simulator that incorporates a linear transistor model for simulating digital MOS circuits. Parallel processing techniques based on the concepts of Virtual Time and rollback are utilized so that portions of the circuit may be simulated on separate processors, in parallel for as large an increase in speed as possible. A partitioning algorithm is also developed in order to subdivide the circuit for parallel processing

The impact of design techniques in the reduction of power consumption of SoCs Multimedia

Orientador: Guido Costa Souza de AraújoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: A indústria de semicondutores sempre enfrentou fortes demandas em resolver problema de dissipação de calor e reduzir o consumo de energia em dispositivos. Esta tendência tem sido intensificada nos últimos anos com o movimento de sustentabilidade ambiental. A concepção correta de um sistema eletrônico de baixo consumo de energia é um problema de vários níveis de complexidade e exige estratégias sistemáticas na sua construção. Fora disso, a adoção de qualquer técnica de redução de energia sempre está vinculada com objetivos especiais e provoca alguns impactos no projeto. Apesar dos projetistas conheçam bem os impactos de forma qualitativa, as detalhes quantitativas ainda são incógnitas ou apenas mantidas dentro do 'know-how' das empresas. Neste trabalho, de acordo com resultados experimentais baseado num plataforma de SoC1 industrial, tentamos quantificar os impactos derivados do uso de técnicas de redução de consumo de energia. Nos concentramos em relacionar o fator de redução de energia de cada técnica aos impactos em termo de área, desempenho, esforço de implementação e verificação. Na ausência desse tipo de dados, que relacionam o esforço de engenharia com as metas de consumo de energia, incertezas e atrasos serão frequentes no cronograma de projeto. Esperamos que este tipo de orientações possam ajudar/guiar os arquitetos de projeto em selecionar as técnicas adequadas para reduzir o consumo de energia dentro do alcance de orçamento e cronograma de projetoAbstract: The semiconductor industry has always faced strong demands to solve the problem of heat dissipation and reduce the power consumption in electronic devices. This trend has been increased in recent years with the action of environmental sustainability. The correct conception of an electronic system for low power consumption is an issue with multiple levels of complexities and requires systematic approaches in its construction. However, the adoption of any technique for reducing the power consumption is always linked with some specific goals and causes some impacts on the project. Although the designers know well that these impacts can affect the design in a quality aspect, the quantitative details are still unkown or just be kept inside the company's know-how. In this work, according to the experimental results based on an industrial SoC2 platform, we try to quantify the impacts of the use of low power techniques. We will relate the power reduction factor of each technique to the impact in terms of area, performance, implementation and verification effort. In the absence of such data, which relates the engineering effort to the goals of power consumption, uncertainties and delays are frequent. We hope that such guidelines can help/guide the project architects in selecting the appropriate techniques to reduce the power consumption within the limit of budget and project scheduleMestradoCiência da ComputaçãoMestre em Ciência da Computaçã

Improving fault tolerant drives for aerospace applications

D EngThe aerospace industry is moving towards the more electric aeroplane where traditional hydraulic systems are being replaced with electrical systems. Electrical technology offers some strong advantages compared to hydraulic technology including; cost, efficiency, power on demand and relative ease of maintenance. As with most new technologies, a major disadvantage is its limited reliability history. A lot of research in the aerospace field therefore focuses on improving fault tolerant electrical systems. Work done in this thesis builds on an existing fault tolerant drive, developed by Newcastle University and Goodrich Actuation Systems as part of the ELGEAR (Electrical Landing Gear) project. The purpose of this work is to continue improving the drive’s fault tolerant features; especially in areas where the drive is most vulnerable. The first part of this thesis focuses on improving the overall system reliability by monitoring the health of the dc-link capacitors in the fault tolerant drive. The implemented estimation technique makes use of voltage and current sensors which are already in place for protection and control purposes. The novel aspect of the proposed technique relates to monitoring capacitors in real time whilst the motor is operational. No external interferences, such as injected signals or special operation of the drive, are required. The condition monitoring system is independent of torque and speed, and hence independent of a variation in load. The work was validated using analytical methods, simulation, low voltage experimentation and high voltage implementation on the ELGEAR drive. The second part of this thesis focuses on single shorted turn faults, in fault tolerant permanent magnet (PM) motors. Despite the motor being able to withstand a wide range of faults, the single shorted turn fault remains a difficult fault to detect and handle. The problem arises from the magnets on the spinning rotor that cannot be ‘turned off’ at will. This thesis investigates the severity of the faulted current in a shorted turn and how it varies depending on the turn’s location in the stator slot. The severity of the fault is studied using 2D finite element analysis and practical implementation on the ELGEAR rig. Finally, recommendations are proposed for improving the ELGEAR motor for future fault tolerant designs.EPRSC and Goodrich Aerospace (now United Technologies

Design of LCOS microdisplay backplanes for projection applications

De evolutie van licht emitterende diodes (LED) heeft ervoor gezorgd dat het op dit moment interessant wordt om deze componenten als lichtbron te gebruiken in projectiesystemen. LED’s hebben belangrijke voordelen vergeleken met klassieke booglampen. Ze zijn compact, ze hebben een veel grotere levensduur en ogenblikkelijke schakeltijden, ze werken op lage spanningen, etc. LED’s zijn smalbandig en kunnen een groterekleurenbereik realiseren. Ze hebben momenteel echter een beperkte helderheid. Naast de lichtbron is het type van de lichtklep ook bepalend voor de kwaliteit van een projectiesysteem. Er bestaan verschillende lichtkleptechnologieën waaronder die van de reflectieve LCOS-panelen. Deze lichtkleppen kunnen zeer hoge resoluties hebben en wordenvaak gebruikt in kwalitatieve, professionele projectiesystemen. LED’s zijn echter totaal verschillend van booglampen. Ze hebben een andere vorm, package, stralingspatroon, aansturing, fysische en thermische eigenschappen, etc. Hoewel er een twintigtal optische architecturen bekend zijn voor reflectieve beeldschermen (met een booglamp als lichtbron), zijn ze niet geschikt voor LED-projectoren en moeten nieuwe optische architecturen en een elektronische aansturing ontwikkeld worden. In dit doctoraat werd er hieromtrent onderzoek gedaan. Er werd uiteindelijk een driekleurenprojector (R, G, B) met een efficiënt LED-belichtingssysteem gebouwd met twee LCOS-lichtkleppen. Deze LEDprojector heeft superieure eigenschappen (zeer lange levensduur, beeldkwaliteit, etc.) en een matige lichtopbrengst

Near-Threshold Computing: Past, Present, and Future.

Transistor threshold voltages have stagnated in recent years, deviating from constant-voltage scaling theory and directly limiting supply voltage scaling. To overcome the resulting energy and power dissipation barriers, energy efficiency can be improved through aggressive voltage scaling, and there has been increased interest in operating at near-threshold computing (NTC) supply voltages. In this region sizable energy gains are achieved with moderate performance loss, some of which can be regained through parallelism. This thesis first provides a methodical definition of how near to threshold is "near threshold" and continues with an in-depth examination of NTC across past, present, and future CMOS technologies. By systematically defining near-threshold, the trends and tradeoffs are analyzed, lending insight in how best to design and optimize near-threshold systems. NTC works best for technologies that feature good circuit delay scalability, therefore technologies without strong short-channel effects. Early planar technologies (prior to 90nm or so) featured good circuit scalability (8x energy gains), but lacked area in which to add cores for parallelization. Recent planar nodes (32nm – 20nm) feature more area for cores but suffer from poor delay scalability, and so are not well-suited for NTC (4x energy gains). The switch to FinFET CMOS technology allows for a return to strong voltage scalability (8x gain), reversing trends seen in planar technologies, while dark silicon has created an opportunity to add cores for parallelization. Improved FinFET voltage scalability even allows for latency reduction of a single task, as long as the task is sufficiently parallelizable (< 10% serial code). Finally, we will look at a technique for fast voltage boosting, called Shortstop, in which a core's operating voltage is raised in 10s of cycles. Shortstop can be used to quickly respond to single-threaded performance demands of a near-threshold system by leveraging the innate parasitic inductance of a dedicated dirty supply rail, further improving energy efficiency. The technique is demonstrated in a wirebond implementation and is able to boost a core up to 1.8x faster than a header-based approach, while reducing supply droop by 2-7x. An improved flip-chip architecture is also proposed.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113600/1/npfet_1.pd