A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

ACOTES project: Advanced compiler technologies for embedded streaming

Streaming applications are built of data-driven, computational components, consuming and producing unbounded data streams. Streaming oriented systems have become dominant in a wide range of domains, including embedded applications and DSPs. However, programming efficiently for streaming architectures is a challenging task, having to carefully partition the computation and map it to processes in a way that best matches the underlying streaming architecture, taking into account the distributed resources (memory, processing, real-time requirements) and communication overheads (processing and delay). These challenges have led to a number of suggested solutions, whose goal is to improve the programmer’s productivity in developing applications that process massive streams of data on programmable, parallel embedded architectures. StreamIt is one such example. Another more recent approach is that developed by the ACOTES project (Advanced Compiler Technologies for Embedded Streaming). The ACOTES approach for streaming applications consists of compiler-assisted mapping of streaming tasks to highly parallel systems in order to maximize cost-effectiveness, both in terms of energy and in terms of design effort. The analysis and transformation techniques automate large parts of the partitioning and mapping process, based on the properties of the application domain, on the quantitative information about the target systems, and on programmer directives. This paper presents the outcomes of the ACOTES project, a 3-year collaborative work of industrial (NXP, ST, IBM, Silicon Hive, NOKIA) and academic (UPC, INRIA, MINES ParisTech) partners, and advocates the use of Advanced Compiler Technologies that we developed to support Embedded Streaming.Peer ReviewedPostprint (published version

Ultra-low loss hybrid ITO/Si thermo-optic phase shifter with optimized power consumption

© 2020 Optical Society of America. One print or electronic copy may be made for personal use only. Systematic reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modifications of the content of this paper are prohibited"[EN] Typically, materials with large optical losses such as metals are used as microheaters for silicon based thermo-optic phase shifters. Consequently, the heater must be placed far from the waveguide, which could come at the expense of the phase shifter performance. Reducing the gap between the waveguide and the heater allows reducing the power consumption or increasing the switching speed. In this work, we propose an ultra-low loss microheater for thermo-optic tuning by using a CMOS-compatible transparent conducting oxide such as indium tin oxide (ITO) with the aim of drastically reducing the gap. Using finite element method simulations, ITO and Ti based heaters are compared for different cladding configurations and TE and TM polarizations. Furthermore, the proposed ITO based microheaters have also been fabricated using the optimum gap and cladding configuration. Experimental results show power consumption to achieve a pi phase shift of 10 mW and switching time of a few microseconds for a 50 mu m long ITO heater. The obtained results demonstrate the potential of using ITO as an ultra-low loss microheater for high performance silicon thermo-optic tuning and open an alternative way for enabling the large-scale integration of phase shifters required in emerging integrated photonic applications. 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Polarization-insensitive mode-independent thermo-optic switch based on symmetric waveguide directional coupler. Optics Express, 27(24), 35385. doi:10.1364/oe.27.035385Atabaki, A. H., Shah Hosseini, E., Eftekhar, A. A., Yegnanarayanan, S., & Adibi, A. (2010). Optimization of metallic microheaters for high-speed reconfigurable silicon photonics. Optics Express, 18(17), 18312. doi:10.1364/oe.18.018312Yu, L., Yin, Y., Shi, Y., Dai, D., & He, S. (2016). Thermally tunable silicon photonic microdisk resonator with transparent graphene nanoheaters. Optica, 3(2), 159. doi:10.1364/optica.3.000159Schall, D., Mohsin, M., Sagade, A. A., Otto, M., Chmielak, B., Suckow, S., … Kurz, H. (2016). Infrared transparent graphene heater for silicon photonic integrated circuits. Optics Express, 24(8), 7871. doi:10.1364/oe.24.007871Yan, S., Zhu, X., Frandsen, L. H., Xiao, S., Mortensen, N. A., Dong, J., & Ding, Y. (2017). Slow-light-enhanced energy efficiency for graphene microheaters on silicon photonic crystal waveguides. Nature Communications, 8(1). doi:10.1038/ncomms14411Xu, Z., Qiu, C., Yang, Y., Zhu, Q., Jiang, X., Zhang, Y., … Su, Y. (2017). Ultra-compact tunable silicon nanobeam cavity with an energy-efficient graphene micro-heater. Optics Express, 25(16), 19479. doi:10.1364/oe.25.019479Lv, J., Yang, Y., Lin, B., Cao, Y., Zhang, Y., Li, S., … Zhang, D. (2019). Graphene-embedded first-order mode polymer Mach–Zender interferometer thermo-optic switch with low power consumption. Optics Letters, 44(18), 4606. doi:10.1364/ol.44.004606Wang, X., Jin, W., Chang, Z., & Chiang, K. S. (2019). Buried graphene electrode heater for a polymer waveguide thermo-optic device. Optics Letters, 44(6), 1480. doi:10.1364/ol.44.001480Lee, D.-J., Kim, H.-M., Kwon, J.-Y., Choi, H., Kim, S.-H., & Kim, K.-B. (2010). Structural and Electrical Properties of Atomic Layer Deposited Al-Doped ZnO Films. Advanced Functional Materials, 21(3), 448-455. doi:10.1002/adfm.201001342Cleary, J. W., Smith, E. M., Leedy, K. D., Grzybowski, G., & Guo, J. (2018). Optical and electrical properties of ultra-thin indium tin oxide nanofilms on silicon for infrared photonics. Optical Materials Express, 8(5), 1231. doi:10.1364/ome.8.001231Ray, S., Banerjee, R., Basu, N., Batabyal, A. K., & Barua, A. K. (1983). Properties of tin doped indium oxide thin films prepared by magnetron sputtering. Journal of Applied Physics, 54(6), 3497-3501. doi:10.1063/1.332415Babicheva, V. E., Kinsey, N., Naik, G. V., Ferrera, M., Lavrinenko, A. V., Shalaev, V. M., & Boltasseva, A. (2013). Towards CMOS-compatible nanophotonics: Ultra-compact modulators using alternative plasmonic materials. Optics Express, 21(22), 27326. doi:10.1364/oe.21.027326Sorger, V. J., Lanzillotti-Kimura, N. D., Ma, R.-M., & Zhang, X. (2012). Ultra-compact silicon nanophotonic modulator with broadband response. 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Thermal effect analysis of silicon microring optical switch for on-chip interconnect. Journal of Semiconductors, 38(10), 104004. doi:10.1088/1674-4926/38/10/10400

Modelling and Co-simulation of Multi-Energy Systems: Distributed Software Methods and Platforms

L'abstract è presente nell'allegato / the abstract is in the attachmen

Towards a scalable and reliable wireless network-on-chip

Multi-core platforms are emerging trends in the design of Systems-on-Chip (SoCs). Interconnect fabrics for these multi-core SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multi-core SoCs. But the performance requirements of NoC infrastructures in future technology nodes cannot be met by relying only on material innovation with traditional scaling. The continuing demand for low power and high speed interconnects with technology scaling necessitates looking beyond the conventional planar metal/dielectric-based interconnect infrastructures. Among different possible alternatives, the on-chip wireless communication network is envisioned as a revolutionary methodology, capable of bringing significant performance gains for multi-core SoCs. Wireless NoCs (WiNoCs) can be designed by using miniaturized on-chip antennas as an enabling technology. In this work, design methodologies and technology requirements for scalable WiNoC architectures are presented and their performance is evaluated. It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude under various experimental and real-life scenarios. A major challenge that NoC design is expected to face is related to the intrinsic unreliability of the interconnect infrastructure under technology limitations. The devices and components of the WiNoCs are expected to suffer high failure rates. By incorporating error control coding (ECC) schemes along the interconnects, NoC architectures will be able to provide correct functionality even in the presence of different sources of transient noise and yet have low energy dissipation. In this work, designs of novel joint crosstalk avoidance and multiple error correction/detection codes as well as burst error correction codes are proposed and their performance is evaluated in different WiNoC fabrics. It is demonstrated that by using the proposed codes WiNoCs can achieve the same reliability as a wireline NoC with much less energy dissipation and higher performance

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book