Principles, fundamentals, and applications of programmable integrated photonics

[EN] Programmable integrated photonics is an emerging new paradigm that aims at designing common integrated optical hardware resource configurations, capable of implementing an unconstrained variety of functionalities by suitable programming, following a parallel but not identical path to that of integrated electronics in the past two decades of the last century. Programmable integrated photonics is raising considerable interest, as it is driven by the surge of a considerable number of new applications in the fields of telecommunications, quantum information processing, sensing, and neurophotonics, calling for flexible, reconfigurable, low-cost, compact, and low-power-consuming devices that can cooperate with integrated electronic devices to overcome the limitation expected by the demise of Moore¿s Law. Integrated photonic devices exploiting full programmability are expected to scale from application-specific photonic chips (featuring a relatively low number of functionalities) up to very complex application-agnostic complex subsystems much in the same way as field programmable gate arrays and microprocessors operate in electronics. Two main differences need to be considered. First, as opposed to integrated electronics, programmable integrated photonics will carry analog operations over the signals to be processed. Second, the scale of integration density will be several orders of magnitude smaller due to the physical limitations imposed by the wavelength ratio of electrons and light wave photons. The success of programmable integrated photonics will depend on leveraging the properties of integrated photonic devices and, in particular, on research into suitable interconnection hardware architectures that can offer a very high spatial regularity as well as the possibility of independently setting (with a very low power consumption) the interconnection state of each connecting element. Integrated multiport interferometers and waveguide meshes provide regular and periodic geometries, formed by replicating unit elements and cells, respectively. In the case of waveguide meshes, the cells can take the form of a square, hexagon, or triangle, among other configurations. Each side of the cell is formed by two integrated waveguides connected by means of a Mach¿Zehnder interferometer or a tunable directional coupler that can be operated by means of an output control signal as a crossbar switch or as a variable coupler with independent power division ratio and phase shift. In this paper, we provide the basic foundations and principles behind the construction of these complex programmable circuits. We also review some practical aspects that limit the programming and scalability of programmable integrated photonics and provide an overview of some of the most salient applications demonstrated so far.European Research Council; Conselleria d'Educació, Investigació, Cultura i Esport; Ministerio de Ciencia, Innovación y Universidades; European Cooperation in Science and Technology; Horizon 2020 Framework Programme.Pérez-López, D.; Gasulla Mestre, I.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Principles, fundamentals, and applications of programmable integrated photonics. Advances in Optics and Photonics. 12(3):709-786. https://doi.org/10.1364/AOP.387155709786123Lyke, J. C., Christodoulou, C. G., Vera, G. A., & Edwards, A. H. (2015). An Introduction to Reconfigurable Systems. Proceedings of the IEEE, 103(3), 291-317. doi:10.1109/jproc.2015.2397832Kaeslin, H. (2008). Digital Integrated Circuit Design. doi:10.1017/cbo9780511805172Trimberger, S. M. (2015). Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology. Proceedings of the IEEE, 103(3), 318-331. doi:10.1109/jproc.2015.2392104Mitola, J. (1995). The software radio architecture. IEEE Communications Magazine, 33(5), 26-38. doi:10.1109/35.393001Nunes, B. A. A., Mendonca, M., Nguyen, X.-N., Obraczka, K., & Turletti, T. (2014). A Survey of Software-Defined Networking: Past, Present, and Future of Programmable Networks. IEEE Communications Surveys & Tutorials, 16(3), 1617-1634. doi:10.1109/surv.2014.012214.00180Papagianni, C., Leivadeas, A., Papavassiliou, S., Maglaris, V., Cervello-Pastor, C., & Monje, A. (2013). On the optimal allocation of virtual resources in cloud computing networks. IEEE Transactions on Computers, 62(6), 1060-1071. doi:10.1109/tc.2013.31Peruzzo, A., Laing, A., Politi, A., Rudolph, T., & O’Brien, J. L. (2011). Multimode quantum interference of photons in multiport integrated devices. Nature Communications, 2(1). doi:10.1038/ncomms1228Metcalf, B. J., Thomas-Peter, N., Spring, J. B., Kundys, D., Broome, M. A., Humphreys, P. C., … Walmsley, I. A. (2013). Multiphoton quantum interference in a multiport integrated photonic device. Nature Communications, 4(1). doi:10.1038/ncomms2349Miller, D. A. B. (2013). Self-aligning universal beam coupler. Optics Express, 21(5), 6360. doi:10.1364/oe.21.006360Miller, D. A. B. (2013). Self-configuring universal linear optical component [Invited]. Photonics Research, 1(1), 1. doi:10.1364/prj.1.000001Carolan, J., Harrold, C., Sparrow, C., Martín-López, E., Russell, N. J., Silverstone, J. W., … Laing, A. (2015). Universal linear optics. Science, 349(6249), 711-716. doi:10.1126/science.aab3642Harris, N. C., Steinbrecher, G. R., Prabhu, M., Lahini, Y., Mower, J., Bunandar, D., … Englund, D. (2017). Quantum transport simulations in a programmable nanophotonic processor. Nature Photonics, 11(7), 447-452. doi:10.1038/nphoton.2017.95Birth of the programmable optical chip. (2015). Nature Photonics, 10(1), 1-1. doi:10.1038/nphoton.2015.265Zhuang, L., Roeloffzen, C. G. H., Hoekman, M., Boller, K.-J., & Lowery, A. J. (2015). Programmable photonic signal processor chip for radiofrequency applications. Optica, 2(10), 854. doi:10.1364/optica.2.000854Pérez, D., Gasulla, I., Capmany, J., & Soref, R. A. (2016). Reconfigurable lattice mesh designs for programmable photonic processors. Optics Express, 24(11), 12093. doi:10.1364/oe.24.012093Capmany, J., Gasulla, I., & Pérez, D. (2015). The programmable processor. Nature Photonics, 10(1), 6-8. doi:10.1038/nphoton.2015.254Pérez, D., Gasulla, I., Crudgington, L., Thomson, D. J., Khokhar, A. Z., Li, K., … Capmany, J. (2017). Multipurpose silicon photonics signal processor core. Nature Communications, 8(1). doi:10.1038/s41467-017-00714-1Clements, W. R., Humphreys, P. C., Metcalf, B. J., Kolthammer, W. S., & Walsmley, I. A. (2016). Optimal design for universal multiport interferometers. Optica, 3(12), 1460. doi:10.1364/optica.3.001460Perez, D., Gasulla, I., Fraile, F. J., Crudgington, L., Thomson, D. J., Khokhar, A. Z., … Capmany, J. (2017). Silicon Photonics Rectangular Universal Interferometer. Laser & Photonics Reviews, 11(6), 1700219. doi:10.1002/lpor.201700219Shen, Y., Harris, N. C., Skirlo, S., Prabhu, M., Baehr-Jones, T., Hochberg, M., … Soljačić, M. (2017). Deep learning with coherent nanophotonic circuits. Nature Photonics, 11(7), 441-446. doi:10.1038/nphoton.2017.93Ribeiro, A., Ruocco, A., Vanacker, L., & Bogaerts, W. (2016). Demonstration of a 4 × 4-port universal linear circuit. Optica, 3(12), 1348. doi:10.1364/optica.3.001348Annoni, A., Guglielmi, E., Carminati, M., Ferrari, G., Sampietro, M., Miller, D. A., … Morichetti, F. (2017). Unscrambling light—automatically undoing strong mixing between modes. Light: Science & Applications, 6(12), e17110-e17110. doi:10.1038/lsa.2017.110Perez, D., Gasulla, I., & Capmany, J. (2018). Toward Programmable Microwave Photonics Processors. Journal of Lightwave Technology, 36(2), 519-532. doi:10.1109/jlt.2017.2778741Chen, L., Hall, E., Theogarajan, L., & Bowers, J. (2011). Photonic Switching for Data Center Applications. IEEE Photonics Journal, 3(5), 834-844. doi:10.1109/jphot.2011.2166994Miller, D. A. B. (2017). Meshing optics with applications. Nature Photonics, 11(7), 403-404. doi:10.1038/nphoton.2017.104Thomas-Peter, N., Langford, N. K., Datta, A., Zhang, L., Smith, B. J., Spring, J. B., … Walmsley, I. A. (2011). Integrated photonic sensing. New Journal of Physics, 13(5), 055024. doi:10.1088/1367-2630/13/5/055024Smit, M., Leijtens, X., Ambrosius, H., Bente, E., van der Tol, J., Smalbrugge, B., … van Veldhoven, R. (2014). An introduction to InP-based generic integration technology. Semiconductor Science and Technology, 29(8), 083001. doi:10.1088/0268-1242/29/8/083001Coldren, L. A., Nicholes, S. C., Johansson, L., Ristic, S., Guzzon, R. S., Norberg, E. J., & Krishnamachari, U. (2011). High Performance InP-Based Photonic ICs—A Tutorial. Journal of Lightwave Technology, 29(4), 554-570. doi:10.1109/jlt.2010.2100807Kish, F., Nagarajan, R., Welch, D., Evans, P., Rossi, J., Pleumeekers, J., … Joyner, C. (2013). From Visible Light-Emitting Diodes to Large-Scale III–V Photonic Integrated Circuits. Proceedings of the IEEE, 101(10), 2255-2270. doi:10.1109/jproc.2013.2275018Hochberg, M., & Baehr-Jones, T. (2010). Towards fabless silicon photonics. Nature Photonics, 4(8), 492-494. doi:10.1038/nphoton.2010.172Bogaerts, W., Fiers, M., & Dumon, P. (2014). Design Challenges in Silicon Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 20(4), 1-8. doi:10.1109/jstqe.2013.2295882Soref, R. (2006). The Past, Present, and Future of Silicon Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 12(6), 1678-1687. doi:10.1109/jstqe.2006.883151Chrostowski, L., & Hochberg, M. (2015). Silicon Photonics Design. doi:10.1017/cbo9781316084168Heck, M. J. R., Bauters, J. F., Davenport, M. L., Doylend, J. K., Jain, S., Kurczveil, G., … Bowers, J. E. (2013). Hybrid Silicon Photonic Integrated Circuit Technology. IEEE Journal of Selected Topics in Quantum Electronics, 19(4), 6100117-6100117. doi:10.1109/jstqe.2012.2235413Keyvaninia, S., Muneeb, M., Stanković, S., Van Veldhoven, P. J., Van Thourhout, D., & Roelkens, G. (2012). Ultra-thin DVS-BCB adhesive bonding of III-V wafers, dies and multiple dies to a patterned silicon-on-insulator substrate. Optical Materials Express, 3(1), 35. doi:10.1364/ome.3.000035Heideman, R., Hoekman, M., & Schreuder, E. (2012). TriPleX-Based Integrated Optical Ring Resonators for Lab-on-a-Chip and Environmental Detection. IEEE Journal of Selected Topics in Quantum Electronics, 18(5), 1583-1596. doi:10.1109/jstqe.2012.2188382Roeloffzen, C. G. H., Zhuang, L., Taddei, C., Leinse, A., Heideman, R. G., van Dijk, P. W. L., … Boller, K.-J. (2013). Silicon nitride microwave photonic circuits. Optics Express, 21(19), 22937. doi:10.1364/oe.21.022937Corbett, B., Loi, R., Zhou, W., Liu, D., & Ma, Z. (2017). Transfer print techniques for heterogeneous integration of photonic components. Progress in Quantum Electronics, 52, 1-17. doi:10.1016/j.pquantelec.2017.01.001Van der Tol, J. J. G. M., Jiao, Y., Shen, L., Millan-Mejia, A., Pogoretskii, V., van Engelen, J. P., & Smit, M. K. (2018). Indium Phosphide Integrated Photonics in Membranes. IEEE Journal of Selected Topics in Quantum Electronics, 24(1), 1-9. doi:10.1109/jstqe.2017.2772786Bachmann, M., Besse, P. A., & Melchior, H. (1994). General self-imaging properties in N × N multimode interference couplers including phase relations. Applied Optics, 33(18), 3905. doi:10.1364/ao.33.003905Soldano, L. B., & Pennings, E. C. M. (1995). Optical multi-mode interference devices based on self-imaging: principles and applications. Journal of Lightwave Technology, 13(4), 615-627. doi:10.1109/50.372474Madsen, C. K., & Zhao, J. H. (1999). Optical Filter Design and Analysis. Wiley Series in Microwave and Optical Engineering. doi:10.1002/0471213756Desurvire, E. (2009). Classical and Quantum Information Theory. doi:10.1017/cbo9780511803758Knill, E., Laflamme, R., & Milburn, G. J. (2001). A scheme for efficient quantum computation with linear optics. Nature, 409(6816), 46-52. doi:10.1038/35051009Capmany, J., & Pérez, D. (2020). Programmable Integrated Photonics. doi:10.1093/oso/9780198844402.001.0001Spagnolo, N., Vitelli, C., Bentivegna, M., Brod, D. J., Crespi, A., Flamini, F., … Sciarrino, F. (2014). Experimental validation of photonic boson sampling. Nature Photonics, 8(8), 615-620. doi:10.1038/nphoton.2014.135Mennea, P. L., Clements, W. R., Smith, D. H., Gates, J. C., Metcalf, B. J., Bannerman, R. H. S., … Smith, P. G. R. (2018). Modular linear optical circuits. Optica, 5(9), 1087. doi:10.1364/optica.5.001087Perez-Lopez, D., Sanchez, E., & Capmany, J. (2018). Programmable True Time Delay Lines Using Integrated Waveguide Meshes. Journal of Lightwave Technology, 36(19), 4591-4601. doi:10.1109/jlt.2018.2831008Pérez-López, D., Gutierrez, A. M., Sánchez, E., DasMahapatra, P., & Capmany, J. (2019). Integrated photonic tunable basic units using dual-drive directional couplers. Optics Express, 27(26), 38071. doi:10.1364/oe.27.038071Jinguji, K., & Kawachi, M. (1995). Synthesis of coherent two-port lattice-form optical delay-line circuit. Journal of Lightwave Technology, 13(1), 73-82. doi:10.1109/50.350643Mookherjea, S., & Yariv, A. (2002). Coupled resonator optical waveguides. IEEE Journal of Selected Topics in Quantum Electronics, 8(3), 448-456. doi:10.1109/jstqe.2002.1016347Heebner, J. E., Chak, P., Pereira, S., Sipe, J. E., & Boyd, R. W. (2004). Distributed and localized feedback in microresonator sequences for linear and nonlinear optics. Journal of the Optical Society of America B, 21(10), 1818. doi:10.1364/josab.21.001818Fandiño, J. S., Muñoz, P., Doménech, D., & Capmany, J. (2016). A monolithic integrated photonic microwave filter. Nature Photonics, 11(2), 124-129. doi:10.1038/nphoton.2016.233Miller, D. A. B. (2012). All linear optical devices are mode converters. Optics Express, 20(21), 23985. doi:10.1364/oe.20.023985Brown, S. D., Francis, R. J., Rose, J., & Vranesic, Z. G. (1992). Field-Programmable Gate Arrays. doi:10.1007/978-1-4615-3572-0Lee, E. K. F., & Gulak, P. G. (1992). Field programmable analogue array based on MOSFET transconductors. Electronics Letters, 28(1), 28-29. doi:10.1049/el:19920017Lee, E. K. F., & Gulak, P. G. (s. f.). A transconductor-based field-programmable analog array. Proceedings ISSCC ’95 - International Solid-State Circuits Conference. doi:10.1109/isscc.1995.535521Pérez, D., Gasulla, I., & Capmany, J. (2018). Field-programmable photonic arrays. Optics Express, 26(21), 27265. doi:10.1364/oe.26.027265Zheng, D., Doménech, J. D., Pan, W., Zou, X., Yan, L., & Pérez, D. (2019). Low-loss broadband 5  ×  5 non-blocking Si3N4 optical switch matrix. Optics Letters, 44(11), 2629. doi:10.1364/ol.44.002629Densmore, A., Janz, S., Ma, R., Schmid, J. H., Xu, D.-X., Delâge, A., … Cheben, P. (2009). Compact and low power thermo-optic switch using folded silicon waveguides. Optics Express, 17(13), 10457. doi:10.1364/oe.17.010457Song, M., Long, C. M., Wu, R., Seo, D., Leaird, D. E., & Weiner, A. M. (2011). Reconfigurable and Tunable Flat-Top Microwave Photonic Filters Utilizing Optical Frequency Combs. IEEE Photonics Technology Letters, 23(21), 1618-1620. doi:10.1109/lpt.2011.2165209Rudé, M., Pello, J., Simpson, R. E., Osmond, J., Roelkens, G., van der Tol, J. J. G. M., & Pruneri, V. (2013). Optical switching at 1.55 μm in silicon racetrack resonators using phase change materials. Applied Physics Letters, 103(14), 141119. doi:10.1063/1.4824714Zheng, J., Khanolkar, A., Xu, P., Colburn, S., Deshmukh, S., Myers, J., … Majumdar, A. (2018). GST-on-silicon hybrid nanophotonic integrated circuits: a non-volatile quasi-continuously reprogrammable platform. Optical Materials Express, 8(6), 1551. doi:10.1364/ome.8.001551Edinger, P., Errando-Herranz, C., & Gylfason, K. B. (2019). Low-Loss MEMS Phase Shifter for Large Scale Reconfigurable Silicon Photonics. 2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS). doi:10.1109/memsys.2019.8870616Carroll, L., Lee, J.-S., Scarcella, C., Gradkowski, K., Duperron, M., Lu, H., … O’Brien, P. (2016). Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices. Applied Sciences, 6(12), 426. doi:10.3390/app6120426Bahadori, M., Gazman, A., Janosik, N., Rumley, S., Zhu, Z., Polster, R., … Bergman, K. (2018). Thermal Rectification of Integrated Microheaters for Microring Resonators in Silicon Photonics Platform. Journal of Lightwave Technology, 36(3), 773-788. doi:10.1109/jlt.2017.2781131Cocorullo, G., Della Corte, F. G., Rendina, I., & Sarro, P. M. (1998). Thermo-optic effect exploitation in silicon microstructures. Sensors and Actuators A: Physical, 71(1-2), 19-26. doi:10.1016/s0924-4247(98)00168-xZecevic, N., Hofbauer, M., & Zimmermann, H. (2015). Integrated Pulsewidth Modulation Control for a Scalable Optical Switch Matrix. IEEE Photonics Journal, 7(6), 1-7. doi:10.1109/jphot.2015.2506153Seok, T. J., Quack, N., Han, S., & Wu, M. C. (2015). 50×50 Digital Silicon Photonic Switches with MEMS-Actuated Adiabatic Couplers. Optical Fiber Communication Conference. doi:10.1364/ofc.2015.m2b.4Zortman, W. A., Trotter, D. C., & Watts, M. R. (2010). Silicon photonics manufacturing. Optics Express, 18(23), 23598. doi:10.1364/oe.18.023598Mower, J., Harris, N. C., Steinbrecher, G. R., Lahini, Y., & Englund, D. (2015). High-fidelity quantum state evolution in imperfect photonic integrated circuits. Physical Review A, 92(3). doi:10.1103/physreva.92.032322Pérez, D., & Capmany, J. (2019). Scalable analysis for arbitrary photonic integrated waveguide meshes. Optica, 6(1), 19. doi:10.1364/optica.6.000019Oton, C. J., Manganelli, C., Bontempi, F., Fournier, M., Fowler, D., & Kopp, C. (2016). Silicon photonic waveguide metrology using Mach-Zehnder interferometers. Optics Express, 24(6), 6265. doi:10.1364/oe.24.006265Chen, X., & Bogaerts, W. (2019). A Graph-based Design and Programming Strategy for Reconfigurable Photonic Circuits. 2019 IEEE Photonics Society Summer Topical Meeting Series (SUM). doi:10.1109/phosst.2019.8795068Zibar, D., Wymeersch, H., & Lyubomirsky, I. (2017). Machine learning under the spotlight. Nature Photonics, 11(12), 749-751. doi:10.1038/s41566-017-0058-3Lopez, D. P. (2020). Programmable Integrated Silicon Photonics Waveguide Meshes: Optimized Designs and Control Algorithms. IEEE Journal of Selected Topics in Quantum Electronics, 26(2), 1-12. doi:10.1109/jstqe.2019.2948048Harris, N. C., Bunandar, D., Pant, M., Steinbrecher, G. R., Mower, J., Prabhu, M., … Englund, D. (2016). Large-scale quantum photonic circuits in silicon. Nanophotonics, 5(3), 456-468. doi:10.1515/nanoph-2015-0146Spring, J. B., Metcalf, B. J., Humphreys, P. C., Kolthammer, W. S., Jin, X.-M., Barbieri, M., … Walmsley, I. A. (2012). Boson Sampling on a Photonic Chip. Science, 339(6121), 798-801. doi:10.1126/science.1231692O’Brien, J. L., Furusawa, A., & Vučković, J. (2009). Photonic quantum technologies. Nature Photonics, 3(12), 687-695. doi:10.1038/nphoton.2009.229Kok, P., Munro, W. J., Nemoto, K., Ralph, T. C., Dowling, J. P., & Milburn, G. J. (2007). Linear optical quantum computing with photonic qubits. Reviews of Modern Physics, 79(1), 135-174. doi:10.1103/revmodphys.79.135Politi, A., Cryan, M. J., Rarity, J. G., Yu, S., & O’Brien, J. L. (2008). Silica-on-Silicon Waveguide Quantum Circuits. Science, 320(5876), 646-649. doi:10.1126/science.1155441Politi, A., Matthews, J., Thompson, M. G., & O’Brien, J. L. (2009). Integrated Quantum Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 15(6), 1673-1684. doi:10.1109/jstqe.2009.2026060Thompson, M. G., Politi, A., Matthews, J. C. F., & O’Brien, J. L. (2011). Integrated waveguide circuits for optical quantum computing. IET Circuits, Devices & Systems, 5(2), 94. doi:10.1049/iet-cds.2010.0108Silverstone, J. W., Bonneau, D., O’Brien, J. L., & Thompson, M. G. (2016). Silicon Quantum Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 22(6), 390-402. doi:10.1109/jstqe.2016.2573218Poot, M., Schuck, C., Ma, X., Guo, X., & Tang, H. X. (2016). Design and characterization of integrated components for SiN photonic quantum circuits. Optics Express, 24(7), 6843. doi:10.1364/oe.24.006843Saleh, M. F., Di Giuseppe, G., Saleh, B. E. A., & Teich, M. C. (2010). Modal and polarization qubits in Ti:LiNbO_3 photonic circuits for a universal quantum logic gate. Optics Express, 18(19), 20475. doi:10.1364/oe.18.020475Harris, N. C., Carolan, J., Bunandar, D., Prabhu, M., Hochberg, M., Baehr-Jones, T., … Englund, D. (2018). Linear programmable nanophotonic processors. Optica, 5(12), 1623. doi:10.1364/optica.5.001623Qiang, X., Zhou, X., Wang, J., Wilkes, C. M., Loke, T., O’Gara, S., … Matthews, J. C. F. (2018). Large-scale silicon quantum photonics implementing arbitrary two-qubit processing. Nature Photonics, 12(9), 534-539. doi:10.1038/s41566-018-0236-yLee, B. G., & Dupuis, N. (2019). Silicon Photonic Switch Fabrics: Technology and Architecture. Journal of Lightwave Technology, 37(1), 6-20. doi:10.1109/jlt.2018.2876828Cheng, Q., Rumley, S., Bahadori, M., & Bergman, K. (2018). Photonic switching in high performance datacenters [Invited]. Optics Express, 26(12), 16022. doi:10.1364/oe.26.016022Wonfor, A., Wang, H., Penty, R. V., & White, I. H. (2011). Large Port Count High-Speed Optical Switch Fabric for Use Within Datacenters [Invited]. Journal of Optical Communications and Networking, 3(8), A32. doi:10.1364/jocn.3.000a32Hamamoto, K., Anan, T., Komatsu, K., Sugimoto, M., & Mito, I. (1992). First 8×8 semiconductor optical matrix switches using GaAs/AlGaAs electro-optic guided-wave directional couplers. Electronics Letters, 28(5), 441. doi:10.1049/el:19920278Van Campenhout, J., Green, W. M., Assefa, S., & Vlasov, Y. A. (2009). Low-power, 2×2 silicon electro-optic switch with 110-nm bandwidth for broadband reconfigurable optical networks. Optics Express, 17(26), 24020. doi:10.1364/oe.17.024020Dupuis, N., Lee, B. G., Rylyakov, A. V., Kuchta, D. M., Baks, C. W., Orcutt, J. S., … Schow, C. L. (2015). D

DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips

To understand and improve DRAM performance, reliability, security and energy efficiency, prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art open source infrastructures capable of conducting such studies are obsolete, poorly supported, or difficult to use, or their inflexibility limit the types of studies they can conduct. We propose DRAM Bender, a new FPGA-based infrastructure that enables experimental studies on state-of-the-art DRAM chips. DRAM Bender offers three key features at the same time. First, DRAM Bender enables directly interfacing with a DRAM chip through its low-level interface. This allows users to issue DRAM commands in arbitrary order and with finer-grained time intervals compared to other open source infrastructures. Second, DRAM Bender exposes easy-to-use C++ and Python programming interfaces, allowing users to quickly and easily develop different types of DRAM experiments. Third, DRAM Bender is easily extensible. The modular design of DRAM Bender allows extending it to (i) support existing and emerging DRAM interfaces, and (ii) run on new commercial or custom FPGA boards with little effort. To demonstrate that DRAM Bender is a versatile infrastructure, we conduct three case studies, two of which lead to new observations about the DRAM RowHammer vulnerability. In particular, we show that data patterns supported by DRAM Bender uncovers a larger set of bit-flips on a victim row compared to the data patterns commonly used by prior work. We demonstrate the extensibility of DRAM Bender by implementing it on five different FPGAs with DDR4 and DDR3 support. DRAM Bender is freely and openly available at https://github.com/CMU-SAFARI/DRAM-Bender.Comment: To appear in TCAD 202

GROK-FPGA: Generating Real on-Chip Knowledge for FPGA Fine-Grain Delays Using Timing Extraction

Circuit variation is one of the biggest problems to overcome if Moore\u27s Law is to continue. It is no longer possible to maintain an abstraction of identical devices without huge yield losses, performance penalties, and energy costs. Current techniques such as margining and grade binning are used to deal with this problem. However, they tend to be conservative, offering limited solutions that will not scale as variation increases. Conventional circuits use limited tests and statistical models to determine the margining and binning required to counteract variation. If the limited tests fail, the whole chip is discarded. On the other hand, reconfigurable circuits, such as FPGAs, can use more fine-grained, aggressive techniques that carefully choose which resources to use in order to mitigate variation. Knowing which resources to use and avoid, however, requires measurement of underlying variation. We present Timing Extraction, a methodology that allows measurement of process variation without expensive testers nor highly invasive techniques, rather, relying only on resources already available on conventional FPGAs. It takes advantage of the fact that we can measure the delay of logic paths between any two registers. Measuring enough paths, provides the information necessary to decompose the delay of each path into individual components-essentially, forming a system of linear equations. Determining which paths to measure requires simple graph transformation algorithms applied to a representation of the FPGA circuit. Ultimately, this process decomposes the FPGA into individual components and identifies which paths to measure for computing the delay of individual components. We apply Timing Extraction to 18 commercially available Altera Cyclone III (65 nm) FPGAs. We measure 22×28 logic clusters and the interconnect within and between cluster. Timing Extraction decomposes this region into 1,356,182 components, classified into 10 categories, requiring 2,736,556 path measurements. With an accuracy of ±3.2 ps, our measurements reveal regional variation on the order of 50 ps, systematic variation from 30 ps to 70 ps, and random variation in the clusters with σ=15 ps and in the interconnect with σ=62 ps

FPGA Security Techniques with Applications to Cloud and Multi-Tenant Use Cases

Field programmable gate arrays (FPGAs) are integrated circuits that consist of programmable logic that a user can configure and deploy for applications such as hardware emulation and accelerating high performance computing. In recent years, the emergence of FPGAs in the cloud has led to research on multi-tenant FPGAs. In a multi-tenant scenario, the same FPGA fabric is shared among multiple users, or among multiple untrusting IP cores. Multi-tenancy has economic benefits, largely due to improvements in resource utilization, but also brings new security concerns since the tenants could behave maliciously. Although the tenants sharing an FPGA are logically isolated from each other, they may still have unintended interactions through side channel attacks and fault attacks. In this dissertation, we aim to evaluate security threats and defenses in the multi-tenant FPGA scenario. Firstly, the work in this dissertation studies a true random number generator (TRNG) on cloud FPGAs that is robust against voltage manipulation from co-tenants. The TRNG design is based on harvesting clock jitter using a tunable time-to-digital converter circuit. In accordance with best practices, a stochastic model is built to evaluate the min-entropy of the design, and further validated by NIST entropy assessment test suite and NIST statistical tests. The basic version of the TRNG is extended with a linkable sampling module to increase min-entropy per sample and throughput at a modest resource cost. Then the dissertation analyzes a type of fault attack that can be conducted by one tenant against another in a multi-tenant setting. Specifically, the fault attack is differential fault intensity analysis (DFIA), which is a biased-fault based attack on Advanced Encryption Standard (AES) circuits. Ring oscillators (ROs) are deployed as effective power wasters to cause a supply voltage drop through the shared power distribution network (PDN) of tenants. The attack is highly relevant to multi-tenant scenarios because the attacking tenant can create the voltage drop without physical access, and can precisely control the shape of the voltage drop by adjusting both the number of activated ROs and their duration as required for the attack. The voltage drop will in turn increase the delay in the logic and eventually cause specific timing faults which are analyzed to successfully recover the AES keys. In the last part, we use on-chip voltage sensors to detect the location of a target circuits. The sensing scheme leverages time-to-digital converters (TDCs) as voltage sensors, and a novel differential analysis is applied to the sensor data. In a multi-tenant setting, this method can be used either as part of a defensive scheme to monitor against attacks, or it can be used to probe a system and determine how to effectively target an attack to a particular co-tenant victim

Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures

Emulating large complex designs require multi-FPGA systems (MFS). However, inter-FPGA communication is confronted by the challenge of lack of interconnect capacity due to limited number of FPGA input/output (I/O) pins. Serializing parallel signals onto a single trace effectively addresses the limited I/O pin obstacle. Besides the multiplexing scheme and multiplexing ratio (number of inter-FPGA signals per trace), the choice of the MFS routing architecture also affect the critical path latency. The routing architecture of an MFS is the interconnection pattern of FPGAs, fixed wires and/or programmable interconnect chips. Performance of existing MFS routing architectures is also limited by off-chip interface selection. In this dissertation we proposed novel 2D and 3D latency-optimized time-multiplexed MFS routing architectures. We used rigorous experimental approach and real sequential benchmark circuits to evaluate and compare the proposed and existing MFS routing architectures. This research provides a new insight into the encouraging effects of using off-chip optical interface and three dimensional MFS routing architectures. The vertical stacking results in shorter off-chip links improving the overall system frequency with the additional advantage of smaller footprint area. The proposed 3D architectures employed serialized interconnect between intra-plane and inter-plane FPGAs to address the pin limitation problem. Additionally, all off-chip links are replaced by optical fibers that exhibited latency improvement and resulted in faster MFS. Results indicated that exploiting third dimension provided latency and area improvements as compared to 2D MFS. We also proposed latency-optimized planar 2D MFS architectures in which electrical interconnections are replaced by optical interface in same spatial distribution. Performance evaluation and comparison showed that the proposed architectures have reduced critical path delay and system frequency improvement as compared to conventional MFS. We also experimentally evaluated and compared the system performance of three inter-FPGA communication schemes i.e. Logic Multiplexing, SERDES and MGT in conjunction with two routing architectures i.e. Completely Connected Graph (CCG) and TORUS. Experimental results showed that SERDES attained maximum frequency than the other two schemes. However, for very high multiplexing ratios, the performance of SERDES & MGT became comparable

The case for a Hardware Filesystem

As secondary storage devices get faster with flash based solid state drives (SSDs) and emerging technologies like phase change memories (PCM), overheads in system software like operating system (OS) and filesystem become prominent and may limit the potential performance improvements. Moreover, with rapidly increasing on-chip core count, monolithic operating systems will face scalability issues on these many-core chips. Future operating systems are likely to have a distributed nature, with a separation of operating system services amongst cores. Also, general purpose processors are known to be both performance and power inefficient while executing operating system code. In the domain of High Performance Computing with FPGAs too, relying on the OS for file I/O transactions using slow embedded processors, hinders performance. Migrating the filesystem into a dedicated hardware core, has the potential of improving the performance of data-intensive applications by bypassing the OS stack to provide higher bandwdith and reduced latency while accessing disks. To test the feasibility of this idea, an FPGA-based Hardware Filesystem (HWFS) was designed with five basic operations (open, read, write, delete and seek). Furthermore, multi-disk and RAID-0 (striping) support has been implemented as an option in the filesystem. In order to reduce design complexity and facilitate easier testing of the HWFS, a RAM disk was used initially. The filesystem core has been integrated and tested with a hardware application core (BLAST) as well as a multi-node FPGA network to provide remote-disk access. Finally, a SATA IP core was developed and directly integrated with HWFS to test with SSDs. For evaluation, HWFS's performance was compared to an Ext2 filesystem, both on an FPGA-based soft processor as well as a modern AMD Opteron Linux server with sequential and random workloads. Results prove that the Hardware Filesystem and supporting infrastructure provide substantial performance improvement over software only systems. The system is also resource efficient consuming less than 3% of logic and 5% of the Block RAMs of a Xilinx Virtex-6 chip

Review of Fault Mitigation Approaches for Deep Neural Networks for Computer Vision in Autonomous Driving

The aim of this work is to identify and present challenges and risks related to the employment of DNNs in Computer Vision for Autonomous Driving. Nowadays one of the major technological challenges is to choose the right technology among the abundance that is available on the market. Specifically, in this thesis it is collected a synopsis of the state-of-the-art architectures, techniques and methodologies adopted for building fault-tolerant hardware and ensuring robustness in DNNs-based Computer Vision applications for Autonomous Driving

A Physical Unclonable Function Based on Inter-Metal Layer Resistance Variations and an Evaluation of its Temperature and Voltage Stability

Keying material for encryption is stored as digital bistrings in non-volatile memory (NVM) on FPGAs and ASICs in current technologies. However, secrets stored this way are not secure against a determined adversary, who can use probing attacks to steal the secret. Physical Unclonable functions (PUFs) have emerged as an alternative. PUFs leverage random manufacturing variations as the source of entropy for generating random bitstrings, and incorporate an on-chip infrastructure for measuring and digitizing the corresponding variations in key electrical parameters, such as delay or voltage. PUFs are designed to reproduce a bitstring on demand and therefore eliminate the need for on-chip storage. In this dissertation, I propose a kind of PUF that measures resistance variations in inter-metal layers that define the power grid of the chip and evaluate its temperature and voltage stability. First, I introduce two implementations of a power grid-based PUF (PG-PUF). Then, I analyze the quality of bit strings generated without considering environmental variations from the PG-PUFs that leverage resistance variations in: 1) the power grid metal wires in 60 copies of a 90 nm chip and 2) in the power grid metal wires of 58 copies of a 65 nm chip. Next, I carry out a series of experiments in a set of 63 chips in IBM\u27s 90 nm technology at 9 TV corners, i.e., over all combination of 3 temperatures: -40oC, 25oC and 85oC and 3 voltages: nominal and +/-10% of the nominal supply voltage. The randomness, uniqueness and stability characteristics of bitstrings generated from PG-PUFs are evaluated. The stability of the PG-PUF and an on-chip voltage-to-digital (VDC) are also evaluated at 9 temperature-voltage corners. I introduce several techniques that have not been previously described, including a mechanism to eliminate voltage trends or \u27bias\u27 in the power grid voltage measurements, as well as a voltage threshold, Triple-Module-Redundancy (TMR) and majority voting scheme to identify and exclude unstable bits

Single-Laser Multi-Terabit/s Systems

Optical communication systems carry the bulk of all data traffic worldwide. This book introduces multi-Terabit/s transmission systems and three key technologies for next generation networks. A software-defined multi-format transmitter, an optical comb source and an optical processing scheme for the fast Fourier transform for Tbit/s signals. Three world records demonstrate the potential: The first single laser 10 Tbit/s and 26 Tbit/s OFDM and the first 32.5 Tbit/s Nyquist WDM experiments