Printed Circuit Board (PCB) design process and fabrication

This module describes main characteristics of Printed Circuit Boards (PCBs). A brief history of PCBs is introduced in the first chapter. Then, the design processes and the fabrication of PCBs are addressed and finally a study case is presented in the last chapter of the module.Peer ReviewedPostprint (published version

Signal and power integrity co-simulation using the multi-layer finite difference method

Mixed signal system-on-package (SoP) technology is a key enabler for increasing functional integration, especially in mobile and wireless systems. Due to the presence of multiple dissimilar modules, each having unique power supply requirements, the design of the power distribution network (PDN) becomes critical. Typically, this PDN is designed as alternating layers of power and ground planes with signal interconnects routed in between or on top of the planes. The goal for the simulation of multi-layer power/ground planes, is the following: Given a stack-up and other geometrical information, it is required to find the network parameters (S/Y/Z) between port locations. Commercial packages have extremely complicated stack-ups, and the trend to increasing integration at the package level only points to increasing complexity. It is computationally intractable to solve these problems using these existing methods. The approach proposed in this thesis for obtaining the response of the PDN is the multi-layer finite difference method (M-FDM). A surface mesh / finite difference based approach is developed, which leads to a system matrix that is sparse and banded, and can be solved efficiently. The contributions of this research are the following: 1. The development of a PDN modeler for multi-layer packages and boards called the the multi-layer finite difference method. 2. The enhancement of M-FDM using multi-port connection networks to include the effect of fringe fields and gap coupling. 3. An adaptive triangular mesh based scheme called the multi-layer finite element method (MFEM) to address the limitations of M-FDM 4. The use of modal decomposition for the co-simulation of signal nets with the PDN. 5. The use of a robust GA-based optimizer for the selection and placement of decoupling capacitors in multi-layer geometries. 6. Implementation of these methods in a tool called MSDT 1.Ph.D.Committee Chair: Madhavan Swaminathan; Committee Member: Andrew F. Peterson; Committee Member: David C. Keezer; Committee Member: Saibal Mukhopadyay; Committee Member: Suresh Sitarama

Statistical Power Supply Dynamic Noise Prediction in Hierarchical Power Grid and Package Networks

One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, /a priori dynamic voltage drop/evaluation is the focus of this work. It takes into account transient currents and on-chip and package /RLC/ parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable result

On the nature and effect of power distribution noise in CMOS digital integrated circuits

The thesis reports on the development of a novel simulation method aimed at modelling power distribution noise generated in digital CMOS integrated circuits. The simulation method has resulted in new information concerning: 1. The magnitude and nature of the power distribution noise and its dependence on the performance and electrical characteristics of the packaged integrated circuit. Emphasis is laid on the effects of resistive, capacitative and inductive elements associated with the packaged circuit. 2. Power distribution noise associated with a generic systolic array circuit comprising 1,020,000 transistors, of which 510,000 are synchronously active. The circuit is configured as a linear array which, if fabricated using two-micron bulk CMOS technology, would be over eight centimetres long and three millimetres wide. In principle, the array will perform 1.5 x 10 to the power of 11 operations per second. 3. Power distribution noise associated with a non-array-based signal processor which, if fabricated in 2-micron bulk CMOS technology, would occupy 6.7 sq. cm. The circuit contains about 900,000 transistors, of which 600,000 are functional and about 300,000 are used for yield enhancement. The processor uses the RADIX-2 algorithm and is designed to achieve 2 x 10 to the power of 8 floating point operations per second. 4. The extent to which power distribution noise limits the level of integration and/ or performance of such circuits using standard and non-standard fabrication and packaging technology. 5. The extent to which the predicted power distribution noise levels affect circuit susceptibility to transient latch-up and electromigration. It concludes the nature of CMOS digital integrated circuit power distribution noise and recommends ways in which it may be minimised. It outlines an approach aimed at mechanising the developed simulation methodology so that the performance of power distribution networks may more routinely be assessed. Finally. it questions the long term suitability of mainly digital techniques for signal processing

Study and design of an interface for remote audio processing

This project focused on the study and design of an interface for remote audio processing, with the objective of acquiring by filtering, biasing, and amplifying an analog signal before digitizing it by means of two MCP3208 ADCs to achieve a 24-bit resolution signal. The resulting digital signal was then transmitted to a Raspberry Pi using SPI protocol, where it was processed by a Flask server that could be accessed from both local and remote networks. The design of the PCB was a critical component of the project, as it had to accommodate various components and ensure accurate signal acquisition and transmission. The PCB design was created using KiCad software, which allowed for the precise placement and routing of all components. A major challenge in the design of the interface was to ensure that the analog signal was not distorted during acquisition and amplification. This was achieved through careful selection of amplifier components and using high-pass and low-pass filters to remove any unwanted noise. Once the analog signal was acquired and digitized, the resulting digital signal was transmitted to the Raspberry Pi using SPI protocol. The Raspberry Pi acted as the host for a Flask server, which could be accessed from local and remote networks using a web browser. The Flask server allowed for the processing of the digital signal and provided a user interface for controlling the gain and filtering parameters of the analog signal. This enabled the user to adjust the signal parameters to suit their specific requirements, making the interface highly flexible and adaptable to a variety of audio processing applications. The final interface was capable of remote audio processing, making it highly useful in scenarios where the audio signal needed to be acquired and processed in a location separate from the user. For example, it could be used in a recording studio, where the audio signal from the microphone could be remotely processed using the interface. The gain and filtering parameters could be adjusted in real-time, allowing the sound engineer to fine-tune the audio signal to produce the desired recording. In conclusion, the project demonstrated the feasibility and potential benefits of using a remote audio processing system for various applications. The design of the PCB, selection of components, and use of the Flask server enabled the creation of an interface that was highly flexible, accurate, and adaptable to a variety of audio processing requirements. Overall, the project represents a significant step forward in the field of remote audio processing, with the potential to benefit many different applications in the future

High Frequency Signaling Analysis Of Inter-Chip Package Routing For Multi-Chip Package

Multi-Chip Package (MCP) is becoming a customary form of integration in many high performance and advanced electronic devices. The vast adoptions of this technology are mainly contributed by the advantages for instance lower power consumption, heterogeneous integration of multiple silicon process technologies and manufacturers, shorter time-to-market and lower costs. However, the high density inter-chip I/O routing within package will presents unique signaling challenges when coupled with high operating data rate. Tackling the right issue at early design stage is essential to avoid the pitfall of redesign. Thus, with the aim to establish the design guideline to enable high performance MCP channel, this research focuses on the signaling analysis of the inter-chip I/O package routing between silicon devices in MCP. In this study, signal quality and eye margin sensitivity were evaluated from 2.5 GHz up-to 7.5 GHz. The microwave effect is found dominating the transmission line component that resulted in signal quality deteriorations. Key limiting factors such as crosstalk coupling effects, signal reflections and frequency dependent losses that caused signal quality degradations were identified and categorized from 2.5 GHz to 7.5 GHz with channel length of 3 mm to 30 mm for future MCP design considerations. Moreover, various low power passive signaling enhancement techniques i.e. equalization and termination to mitigate the signal integrity challenges of the high speed on-package inter-chip channels has been analyzed