Statistical Power Supply Dynamic Noise Prediction in Hierarchical Power Grid and Package Networks

One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, /a priori dynamic voltage drop/evaluation is the focus of this work. It takes into account transient currents and on-chip and package /RLC/ parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable result

Scaling Trends of On-Chip Power Distribution Noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by, where I, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by in the case of resistive noise and by P in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise

Electrical Characteristics of Multi-Layer Power Distribution Grids

The design of robust and area efficient power distribution networks for high speed, high complexity integrated circuits has become a challenging task. The integrity of the high frequency signals depends upon the impedance characteristics of the on-chip power distribution networks. The electrical characteristics of these multi-layer power distribution grids and the relevant design implications are the subject of this paper. Each grid layer within a multilayer power distribution grid typically has significantly different electrical properties. Unlike single layer grids, the electrical characteristics of a multi-layer grid can vary significantly with frequency. As the frequency increases, a large share of the current flow is transfered from the low resistance upper layers to the low inductance lower layers. The inductance of a multi-layer grid therefore decreases with frequency, while the resistance increases with frequency. Therefore, as compared to power distribution grids built exclusively in the upper, low resistance metal layers, a multi-layer power distribution grid extending to the lower interconnect layers exhibits superior high frequency impedance characteristics. An analytic model is also presented to determine the impedance characteristics of a multi-layer grid from the inductive and resistive properties of the comprising individual grid layers

Inductive Characteristics of Power Distribution Grids In High Speed . . .

The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties provide accurate and efficient estimates of the inductance of power grid structures with various dimensions

Properties of On-Chip Inductive Current Loops

The variation of inductance with circuit length is investigated in this paper. The nonlinear variation of inductance with length is shown to be a result of inductive coupling among circuit segments. If the distance between the forward and return current paths of a current loop is much smaller than the loop length, the inductive coupling to the forward current is similar to the coupling to the return current, resulting in negligible coupling. The inductance of these circuits therefore varies approximately linearly with length. Similarly, the effective inductive coupling between two parallel current loops is reduced through cancellation and has a negligible effect on the net inductance of a circuit. As a general rule, the inductance of circuits where the distance between the forward and return current is much smaller than the characteristic dimensions of the circuit scales linearly with circuit dimensions. This linear behavior can be used to simplify the inductance extraction and circuit analysis process

Scaling Trends of On-Chip Power Distribution Noise

The design of power distribution networks in high performance integrated circuits has become significantly more challenging with recent advances in process technology. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of the on-chip power supply has become a primary concern in integrated circuit design. The existing work on power distribution noise scaling is reviewed and extended to include the scaling of the inductance of the on-chip global power distribution networks in high performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S> 1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S 2 in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling in the global power grid mitigates unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will therefore become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise levels

On-chip power delivery and management

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks