177 research outputs found
Implementation of a 200 MSps 12-bit SAR ADC
Analog-to-digital converters (ADCs) with high conversion frequency, often based on pipelined architectures, are used for measuring instruments, wireless communication and video applications. Successive approximation register (SAR) converters offer a compact and power efficient alternative but the conversion speed is typically designed for lower frequencies. In this thesis a low-power 12-bit 200 MSps SAR ADC based on charge redistribution was designed for a 28 nm CMOS technology. The proposed design uses an efficient SAR algorithm (merged capacitor switching procedure) to reduce power consumption due to capacitor charging by 88 % compared to a conventional design, as well as reducing the total capacitor area by half. Sampling switches were bootstrapped for increased linearity compared to simple transmission gates. Another feature of the low power design is a fully-dynamic comparator which does not require a preamplifier. Pre-layout simulations of the SAR ADC with 800 MHz input frequency shows an SNDR of 64.8 dB, corresponding to an ENOB of 10.5, and an SFDR of 75.3 dB. The total power consumption is 1.77 mW with an estimated value of 500 W for the unimplemented digital logic. Calculation of the Schreier figure-of-merit was done with an input signal at the Nyquist frequency. The simulated SNDR, SFDR and power equals 69.5 dB, 77.3 dB and 1.9 mW respectively, corresponding to a figure-of merit of 176.6 dB.FrÄn analogt till digitalt - snabba och strömsnÄla omvandlare Dagens digitala samhÀlle stÀller höga krav pÄ prestanda och effektivitet. I samarbete med Ericsson i Lund har en krets för signalomvandling utvecklats. Genom smart design uppnÄs hög hastighet och lÄg strömförbrukning som ligger i forskningens framkant. FrÄn analogt till digitalt Ett viktigt byggblock för telekommunikation och videoapplikationer Àr sÄ kallade A/D-omvandlare, som översÀtter mellan analoga signaler (till exempel ljud) och digitala signaler bestÄende av ettor och nollor. En vÀldigt effektiv metod för A/D-omvandling bygger pÄ sÄ kallad successiv approximation. Metoden innebÀr att signalen som ska omvandlas jÀmförs med en referensnivÄ, som stegvis justeras för att nÀrma sig signalens vÀrde. Till slut har man en tillrÀckligt god uppskattning av vÀrdet som ska mÀtas. Just en sÄdan omvandlare har utvecklats med höga krav pÄ hastighet och energiförbrukning. Detta gjordes genom datorsimuleringar av modeller som beskriver kretsen. ReferensnivÄn skapas ofta genom att styra ett nÀtverk som lagrar elektrisk laddning. Omvandlingens noggrannhet, eller upplösning, beror pÄ hur mÄnga nivÄer som finns tillgÀngliga det vill sÀga hur nÀra signalens vÀrde man kan komma. I den designade kretsen finns hela 4096 nivÄer! Det finns mÄnga kÀllor till osÀkerhet i systemet, bland annat hur exakta referensnivÄerna Àr och hur bra jÀmförelsen med insignalen kan göras. Eftersom dessa eventuellt kan leda till en försÀmring av omvandlingens noggrannhet mÄste alla delar i kretsen utformas med detta i Ätanke. Höga hastigheter Eftersom det krÀvs mÄnga steg för referensnivÄn att nÀrma sig signalens vÀrde Àr den maximala omvandlingshastigheten ofta begrÀnsad. Med teknikens utveckling öppnas nya möjligheter i takt med att mikrochippens enskilda komponenter blir snabbare. Modern forskning visar att omvandlare baserade pÄ successiv approximation kan uppnÄ hastigheter pÄ flera miljoner mÀtvÀrden varje sekund, vilket Àven den utvecklade kretsen klarar av. Effektiv design Nya metoder för successiv approximation möjliggör stora besparingar nÀr det gÀller effektförbrukning, till exempel genom att effektivisera upp- och urladdningen av nÀtverket. Genom smÄ Àndringar kunde nÀtverkets energiförbrukning minskas med över 90 % samtidigt som dess area halverades. Eftersom produktionskostnaden för integrerade kretsar Àr hög medför varje minskning av kretsens area att kostnaden sjunker
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Design techniques for low-power SAR ADCs in nano-scale CMOS technologies
This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. To improve the comparatorâs power efficiency, a statistical estimation based comparator noise reduction technique is presented. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR) by estimating the conversion residue. A first prototype ADC in 65nm CMOS has been developed to validate the proposed noise reduction technique. It achieves 4.5 fJ/conv-step Walden figure of merit and 64.5 dB signal-to-noise and distortion ratio (SNDR). In addition, a bidirectional single-side switching technique is developed to reduce the DAC switching power. It can reduce the DAC switching power and the total number of unit capacitors by 86% and 75%, respectively. A second prototype ADC with the proposed switching technique is designed and fabricated in 180nm CMOS technology. It achieves an SNDR of 63.4 dB and consumes only 24 Wat 1MS/s, leading to aWalden figure of merit of 19.9 fJ/conv-step. This thesis also presents an improved loop-unrolled SAR ADC, which works at high frequency with reduced SAR logic power and delay. It employs the bidirectional single-side switching technique to reduce the comparator common-mode voltage variation. In addition, it uses a Vcm-adaptive offset calibration technique which can accurately calibrate comparatorâs offset at its operating Vcm. A prototype ADC designed in 40nm CMOS achieves 35 dB at 700 MS/s sampling rate and consumes only 0.95 mW, leading to a Walden figure of merit of 30 fJ/conv-step.Electrical and Computer Engineerin
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Design Techniques for High-Performance SAR A/D Converters
The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs.
ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach âŒGS/s sampling rates at reasonable power consumption.
Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADCâs SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s.
The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew
calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of âŒGS/s with 10-bit resolution and a power consumption as low as âŒ10mW; specifications that satisfy the requirements of 5G technology
A Capacitance-To-Digital Converter for MEMS Sensors for Smart Applications
The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 mu m CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm(2), which means a pressure resolution of 1 Pa, while consuming 146 mu A from a 1.5 V power supply.This work has been funded by Marie Curie project SIMIC, Grant Agreement No. 610484,
funded by grants from the European Union (Research Executive Agency) and TEC2014-56879-R of CICYT, Spain.Publicad
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Signal acquisition challenges in mobile systems
In recent decades, the advent of mobile computing has changed human lives by providing information that was not available in the past. The mobile computing platform opens a new door to the connected world in which various forms of hand-held and wearable systems are ubiquitous. A single mobile device plays multiple roles and shapes human lives towards a better future. In these systems, sensor-based data acquisition plays an essential role in generating and providing useful information.
The increased number of sensors is embedded in a single device in order to process various signal modalities. In practice, more than 30 data converters are required in designing a mobile system in which the data-converting blocks become among the most power-hungry components in battery-operated systems. Due to the increased variety of sensors, mobile systems are meant to face several obstacles. For example, the increased number of sensors increase system power consumption during the system operation. The increased power consumption directly affects operation time because mobile systems are powered by a limited energy source. Moreover, an increased amount of information also gives rise to bandwidth problems in communication due to the increased volume of data transmission. Also, this system design requires a larger area in a silicon die so that multiple signal paths can be placed without cross-channel interference. Therefore, the system design has presented a challenge in terms of trying to resolve the design constraints such as power consumption, bandwidth usage, storage space, and design complexity issues.
To overcome these obstacles, in this dissertation, efficient data acquisition and processing methods are investigated. Specifically, this thesis considers the problems of energy-efficient sampling and binary event detection.
This dissertation begins by presenting a new signal sampling scheme that enables higher precision signal conversion in compressed-sensing-based signal acquisition. The proposed scheme is based on the popular successive approximation register and employs a modified compressive sensing technique to increase the resolution of successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture. Circuit-level architecture is discussed to implement the proposed scheme using the SAR ADC architecture. A non-uniform quantization scheme is proposed and it improves data quality after data acquisition. The proposed scheme is expected to be used for medium- or high- frequency data conversion.
Secondly, the possibility of using fewer ADCs than channels is studied by leveraging sparse-signal representation and blind-source-separation (BSS) techniques.
In particular, this dissertation examines the problem of using a single ADC or quantizer system for digitizing multi-channel inputs. Mixing and de-mixing strategies are extensively studied for sampling frequency-sparse signals and the proposed multi-channel architecture can be easily implemented using today's analog/mixed-signal circuits.
The third part of this dissertation investigates a binary hypothesis testing problem. In mobile devices such as smartphones and tablet PCs, a major portion of energy is consumed in user interfaces (LCD display and touch input processing). For accurate detection and better user interface, energy-efficient sensing and detection schemes are necessary to manage multiple sensor inputs. A highly efficient detection scheme is presented that can detect binary events reliably with a fraction of the energy consumption required in the conventional energy detection.Electrical and Computer Engineerin
Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers
In the field of radio receivers, down-conversion methods usually rely on one (or more)
explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not
only contribute to the overall power consumption but also have an impact on area and can
compromise the receiverâs performance in terms of noise and linearity. On the other hand,
most ADCs require some sort of reference signal in order to properly digitize an analog
input signal. The implementation of this reference signal usually relies on bandgap
circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this
conventional approach, the work developed in this thesis aims to explore the viability
behind the usage of a variable reference signal. Moreover, it demonstrates that not only
can an input signal be properly digitized, but also shifted up and down in frequency,
effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver
chains can perform double-duty as both a quantizer and a mixing stage. The lesser known
charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs,
is used for a practical implementation, due to its feature of âpre-chargingâ the reference
signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in
a 0.13 ÎŒm CMOS technology validate the proposed technique
A Low-Power, Low-Area 10-Bit SAR ADC with Length-Based Capacitive DAC
A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 ”m^2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the second test chip for performance evaluation, and the test method is explained.
Adviser: Sina Balkir and Michael Hoffma
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