Design and Implementation of Control Techniques of Power Electronic Interfaces for Photovoltaic Power Systems

The aim of this thesis is to scrutinize and develop four state-of-the-art power electronics converter control techniques utilized in various photovoltaic (PV) power conversion schemes accounting for maximum power extraction and efficiency. First, Cascade Proportional and Integral (PI) Controller-Based Robust Model Reference Adaptive Control (MRAC) of a DC-DC boost converter has been designed and investigated. Non-minimum phase behaviour of the boost converter due to right half plane zero constitutes a challenge and its non-linear dynamics complicate the control process while operating in continuous conduction mode (CCM). The proposed control scheme efficiently resolved complications and challenges by using features of cascade PI control loop in combination with properties of MRAC. The accuracy of the proposed control system’s ability to track the desired signals and regulate the plant process variables in the most beneficial and optimised way without delay and overshoot is verified. The experimental results and analysis reveal that the proposed control strategy enhanced the tracking speed two times with considerably improved disturbance rejection. Second, (P)roportional Gain (R)esonant and Gain Scheduled (P)roportional (PR-P) Controller has been designed and investigated. The aim of this controller is to create a variable perturbation size real-time adaptive perturb and observe (P&O) maximum power point tracking (MPPT) algorithm. The proposed control scheme resolved the drawbacks of conventional P&O MPPT method associated with the use of constant perturbation size that leads to a poor transient response and high continuous steady-state oscillations. The prime objective of using the PR-P controller is to utilize inherited properties of the signal produced by the controller’s resonant path and integrate it to update best estimated perturbation that represents the working principle of extremum seeking control (ESC) to use in a P&O algorithm that characterizes the overall system learning-based real time adaptive (RTA). Additionally, utilization of internal dynamics of the PR-P controller overcome the challenges namely, complexity, computational burden, implantation cost and slow tracking performance in association with commonly used soft computing intelligent systems and adaptive control strategies. The experimental results and analysis reveal that the proposed control strategy enhanced the tracking speed five times with reduced steady-state oscillations around maximum power point (MPP) and more than 99% energy extracting efficiency.Third, the interleaved buck converter based photovoltaic (PV) emulator current control has been investigated. A proportional-resonant-proportional (PR-P) controller is designed to resolve the drawbacks of conventional PI controllers in terms of phase management which means balancing currents evenly between active phases to avoid thermally stressing and provide optimal ripple cancellation in the presence of parameter uncertainties. The proposed controller shows superior performance in terms of 10 times faster-converging transient response, zero steady-state error with significant reduction in current ripple. Equal load sharing that constitutes the primary concern in multi-phase converters has been achieved with the proposed controller. Implementing of robust control theory involving comprehensive time and frequency domain analysis reveals 13% improvement in the robust stability margin and 12-degree bigger phase toleration with the PR-P controller. Fourth, a symmetrical pole placement Method-based Unity Proportional Gain Resonant and Gain Scheduled Proportional (PR-P) Controller has been designed and investigated. The proposed PR-P controller resolved the issues associated with the use of the PI controller which are tracking repeating control input signal with zero steady-state and mitigating the 3rd order harmonic component injected into the grid for single-phase PV systems. Additionally, the PR-P controller has overcome the drawbacks of frequency detuning in the grid and increase in the magnitude of odd number harmonics in the system that constitute the common concerns in the implementation of conventional PR controller. Moreover, the unprecedented design process based on changing notch filter dynamics with symmetrical pole placement around resonant frequency overcomes the limitations that are essentially complexity and dependency on the precisely modelled system. The verification and validation process of the proposed control schemes has been conducted using MATLAB/Simulink and implementing MATLAB/Simulink/State flow on dSPACE Real-time-interface (RTI) 1007 processor, DS2004 High-Speed A/D and CP4002 Timing and Digital I/O boards

Fast‐converging robust PR‐P controller designed by using symmetrical pole placement method for current control of interleaved buck converter‐based PV emulator

In this study, the interleaved buck converter-based photovoltaic (PV) emulator current control is presented. A proportional-resonant-proportional (PR-P) controller is designed to resolve the drawbacks of conventional PI controllers in terms of phase management, which means balancing currents evenly between active phases to avoid thermally stressing and provide optimal ripple cancelation in the presence of parameter uncertainties. The resonant path of the controller (PR) with a constant proportional unity gain is designed considering the changing dynamics of a notch filter by pole placement method (adding mutually complementary poles to the notch transfer function) at PWM switching frequency. The proportional gain path (P) of the controller is used to determine the compatibility of the controller with parameter uncertainty of the phases and designed by utilizing loop-shaping method. The proposed controller shows superior performance in terms of 10 times faster-converging transient response, zero steady-state error with significant reduction in current ripple. Equal load sharing that constitutes the primary concern in multiphase converters is achieved with the proposed controller. Implementing of robust control theory involving comprehensive time and frequency domain analysis reveals 13% improvement in the robust stability margin and 12-degree bigger phase toleration with the PR-P controller. In addition to these, the proposed unconventional design process of the controller reduces the computational complexity and provides cost-effectiveness and simple implementation. Moreover, implementing of auxiliary resistor-capacitor (RC) circuits parallel with the inductors to sense the current in each phase removes the need for current measurement sensors that contribute to overall cost of the system

Design and Control of Power Converters 2019

In this book, 20 papers focused on different fields of power electronics are gathered. Approximately half of the papers are focused on different control issues and techniques, ranging from the computer-aided design of digital compensators to more specific approaches such as fuzzy or sliding control techniques. The rest of the papers are focused on the design of novel topologies. The fields in which these controls and topologies are applied are varied: MMCs, photovoltaic systems, supercapacitors and traction systems, LEDs, wireless power transfer, etc

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

Novel load identification techniques and a steady state self-tuning prototype for switching mode power supplies

Control of Switched Mode Power Supplies (SMPS) has been traditionally achieved through analog means with dedicated integrated circuits (ICs). However, as power systems are becoming increasingly complex, the classical concept of control has gradually evolved into the more general problem of power management, demanding functionalities that are hardly achievable in analog controllers. The high flexibility offered by digital controllers and their capability to implement sophisticated control strategies, together with the programmability of controller parameters, make digital control very attractive as an option for improving the features of dcdc converters. On the other side, digital controllers find their major weak point in the achievable dynamic performances of the closed loop system. Indeed, analogto-digital conversion times, computational delays and sampling-related delays strongly limit the small signal closed loop bandwidth of a digitally controlled SMPS. Quantization effects set other severe constraints not known to analog solutions. For these reasons, intensive scientific research activity is addressing the problem of making digital compensator stronger competitors against their analog counterparts in terms of achievable performances. In a wide range of applications, dcdc converters with high efficiency over the whole range of their load values are required. Integrated digital controllers for Switching Mode Power Supplies are gaining growing interest, since it has been shown the feasibility of digital controller ICs specifically developed for high frequency switching converters. One very interesting potential benefit is the use of autotuning of controller parameters (on-line controllers), so that the dynamic response can be set at the software level, independently of output capacitor filters, component variations and ageing. These kind of algorithms are able to identify the output filter configuration (system identification) and then automatically compute the best compensator gains to adjust system margins and bandwidth. In order to be an interesting solution, however, the self-tuning should satisfy two important requirements: it should not heavily affect converter operation under nominal condition and it should be based on a simple and robust algorithm whose complexity does not require a significant increase of the silicon area of the IC controller. The first issue is avoided performing the system identification (SI) with the system open loop configuration, where perturbations can be induced in the system before the start up. Much more challenging is to satisfy this requirement during steady state operations, where perturbations on the output voltage are limited by the regular operations of the converter. The main advantage of steady state SI methods, is the detection of possible non-idealities occurring during the converter operations. In this way, the system dynamics can be consequently adjusted with the compensator parameters tuning. The resource saving issue, requires the development of äd-hocßelf-tuning techniques specifically tailored for integrated digitally controlled converters. Considering the flexibility of digital control, self-tuning algorithms can be studied and easily integrated at hardware level into closed loop SMPS reducing development time and R & D costs. The work of this dissertation finds its origin in this context. Smart power management is accomplished by tuning the controller parameters accordingly to the identified converter configuration. Themain difficult for self-tuning techniques is the identification of the converter output filter configuration. Two novel system identification techniques have been validated in this dissertation. The open loop SI method is based on the system step response, while dithering amplification effects are exploited for the steady state SI method. The open loop method can be used as autotunig approach during or before the system start up, a step evolving reference voltage has been used as system perturbation and to obtain the output filter information with the Power Spectral Density (PSD) computation of the system step response. The use of ¢§ modulator is largely increasing in digital control feedback. During the steady state, the finite resolution introduces quantization effects on the signal path causing low frequency contributes of the digital control word. Through oversampling-dithering capabilities of ¢§ modulators, resolution improvements are obtained. The presented steady state identification techniques demonstrates that, amplifying the dithering effects on the signal path, the output filter information can be obtained on the digital side by processing with the PSD computation the perturbed output voltage. The amount of noise added on the output voltage does not affect the converter operations, mathematical considerations have been addressed and then justified both with a Matlab/Simulink fixed-point and a FPGA-based closed loop system. The load output filter identification of both algorithms, refer to the frequency domain. When the respective perturbations occurs, the system response is observed on the digital side and processed with the PSD computation. The extracted parameters are the resonant frequency ans the possible ESR (Effective Series Resistance) contributes,which can be detected as maximumin the PSD output. The SI methods have been validated for different configurations of buck converters on a fixed-point closed loop model, however, they can be easily applied to further converter configurations. The steady state method has been successfully integrated into a FPGA-based prototype for digitally controlled buck converters, that integrates a PSD computer needed for the load parameters identification. At this purpose, a novel VHDL-coded full-scalable hybrid processor for Constant Geometry FFT (CG-FFT) computation has been designed and integrated into the PSD computation system. The processor is based on a variation of the conventional algorithm used for FFT, which is the Constant-Geometry FFT (CG-FFT).Hybrid CORDIC-LUT scalable architectures, has been introduced as alternative approach for the twiddle factors (phase factors) computation needed during the FFT algorithms execution. The shared core architecture uses a single phase rotator to satisfy all TF requests. It can achieve improved logic saving by trading off with computational speed. The pipelined architecture is composed of a number of stages equal to the number of PEs and achieves the highest possible throughput, at the expense of more hardware usage

FPGAs in Industrial Control Applications

The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs

Novel load identification techniques and a steady state self-tuning prototype for switching mode power supplies

Control of Switched Mode Power Supplies (SMPS) has been traditionally achieved through analog means with dedicated integrated circuits (ICs). However, as power systems are becoming increasingly complex, the classical concept of control has gradually evolved into the more general problem of power management, demanding functionalities that are hardly achievable in analog controllers. The high flexibility offered by digital controllers and their capability to implement sophisticated control strategies, together with the programmability of controller parameters, make digital control very attractive as an option for improving the features of dcdc converters. On the other side, digital controllers find their major weak point in the achievable dynamic performances of the closed loop system. Indeed, analogto-digital conversion times, computational delays and sampling-related delays strongly limit the small signal closed loop bandwidth of a digitally controlled SMPS. Quantization effects set other severe constraints not known to analog solutions. For these reasons, intensive scientific research activity is addressing the problem of making digital compensator stronger competitors against their analog counterparts in terms of achievable performances. In a wide range of applications, dcdc converters with high efficiency over the whole range of their load values are required. Integrated digital controllers for Switching Mode Power Supplies are gaining growing interest, since it has been shown the feasibility of digital controller ICs specifically developed for high frequency switching converters. One very interesting potential benefit is the use of autotuning of controller parameters (on-line controllers), so that the dynamic response can be set at the software level, independently of output capacitor filters, component variations and ageing. These kind of algorithms are able to identify the output filter configuration (system identification) and then automatically compute the best compensator gains to adjust system margins and bandwidth. In order to be an interesting solution, however, the self-tuning should satisfy two important requirements: it should not heavily affect converter operation under nominal condition and it should be based on a simple and robust algorithm whose complexity does not require a significant increase of the silicon area of the IC controller. The first issue is avoided performing the system identification (SI) with the system open loop configuration, where perturbations can be induced in the system before the start up. Much more challenging is to satisfy this requirement during steady state operations, where perturbations on the output voltage are limited by the regular operations of the converter. The main advantage of steady state SI methods, is the detection of possible non-idealities occurring during the converter operations. In this way, the system dynamics can be consequently adjusted with the compensator parameters tuning. The resource saving issue, requires the development of äd-hocßelf-tuning techniques specifically tailored for integrated digitally controlled converters. Considering the flexibility of digital control, self-tuning algorithms can be studied and easily integrated at hardware level into closed loop SMPS reducing development time and R & D costs. The work of this dissertation finds its origin in this context. Smart power management is accomplished by tuning the controller parameters accordingly to the identified converter configuration. Themain difficult for self-tuning techniques is the identification of the converter output filter configuration. Two novel system identification techniques have been validated in this dissertation. The open loop SI method is based on the system step response, while dithering amplification effects are exploited for the steady state SI method. The open loop method can be used as autotunig approach during or before the system start up, a step evolving reference voltage has been used as system perturbation and to obtain the output filter information with the Power Spectral Density (PSD) computation of the system step response. The use of ¢§ modulator is largely increasing in digital control feedback. During the steady state, the finite resolution introduces quantization effects on the signal path causing low frequency contributes of the digital control word. Through oversampling-dithering capabilities of ¢§ modulators, resolution improvements are obtained. The presented steady state identification techniques demonstrates that, amplifying the dithering effects on the signal path, the output filter information can be obtained on the digital side by processing with the PSD computation the perturbed output voltage. The amount of noise added on the output voltage does not affect the converter operations, mathematical considerations have been addressed and then justified both with a Matlab/Simulink fixed-point and a FPGA-based closed loop system. The load output filter identification of both algorithms, refer to the frequency domain. When the respective perturbations occurs, the system response is observed on the digital side and processed with the PSD computation. The extracted parameters are the resonant frequency ans the possible ESR (Effective Series Resistance) contributes,which can be detected as maximumin the PSD output. The SI methods have been validated for different configurations of buck converters on a fixed-point closed loop model, however, they can be easily applied to further converter configurations. The steady state method has been successfully integrated into a FPGA-based prototype for digitally controlled buck converters, that integrates a PSD computer needed for the load parameters identification. At this purpose, a novel VHDL-coded full-scalable hybrid processor for Constant Geometry FFT (CG-FFT) computation has been designed and integrated into the PSD computation system. The processor is based on a variation of the conventional algorithm used for FFT, which is the Constant-Geometry FFT (CG-FFT).Hybrid CORDIC-LUT scalable architectures, has been introduced as alternative approach for the twiddle factors (phase factors) computation needed during the FFT algorithms execution. The shared core architecture uses a single phase rotator to satisfy all TF requests. It can achieve improved logic saving by trading off with computational speed. The pipelined architecture is composed of a number of stages equal to the number of PEs and achieves the highest possible throughput, at the expense of more hardware usage

Grid-Connected Renewable Energy Sources

The use of renewable energy sources (RESs) is a need of global society. This editorial, and its associated Special Issue “Grid-Connected Renewable Energy Sources”, offers a compilation of some of the recent advances in the analysis of current power systems that are composed after the high penetration of distributed generation (DG) with different RESs. The focus is on both new control configurations and on novel methodologies for the optimal placement and sizing of DG. The eleven accepted papers certainly provide a good contribution to control deployments and methodologies for the allocation and sizing of DG