The Design and Implementation of an Extensible Brain-Computer Interface

An implantable brain computer interface: BCI) includes tissue interface hardware, signal conditioning circuitry, analog-to-digital conversion: ADC) circuitry and some sort of computing hardware to discriminate desired waveforms from noise. Within an experimental paradigm the tissue interface and ADC hardware will rarely change. Recent literature suggests it is often the specific implementation of waveform discrimination that can limit the usefulness and lifespan of a particular BCI design. If the discrimination techniques are implemented in on-board software, experimenters gain a level of flexibility not currently available in published designs. To this end, I have developed a firmware library to acquire data sampled from an ADC, discriminate the signal for desired waveforms employing a user-defined function, and perform arbitrary tasks. I then used this design to develop an embedded BCI built upon the popular Texas Instruments MSP430 microcontroller platform. This system can operate on multiple channels simultaneously and is not fundamentally limited in the number of channels that can be processed. The resulting system represents a viable platform that can ease the design, development and use of BCI devices for a variety of applications

Optimizing Harris Corner Detection on GPGPUs Using CUDA

ABSTRACT Optimizing Harris Corner Detection on GPGPUs Using CUDA The objective of this thesis is to optimize the Harris corner detection algorithm implementation on NVIDIA GPGPUs using the CUDA software platform and measure the performance benefit. The Harris corner detection algorithm—developed by C. Harris and M. Stephens—discovers well defined corner points within an image. The corner detection implementation has been proven to be computationally intensive, thus realtime performance is difficult with a sequential software implementation. This thesis decomposes the Harris corner detection algorithm into a set of parallel stages, each of which are implemented and optimized on the CUDA platform. The performance results show that by applying strategic CUDA optimizations to the Harris corner detection implementation, realtime performance is feasible. The optimized CUDA implementation of the Harris corner detection algorithm showed significant speedup over several platforms: standard C, MATLAB, and OpenCV. The optimized CUDA implementation of the Harris corner detection algorithm was then applied to a feature matching computer vision system, which showed significant speedup over the other platforms

A multiprocessor implementation of a contextual image processing algorithm

There are no author-identified significant results in this report

Processing techniques development, volume 3. Part 2: Data preprocessing and information extraction techniques

There are no author-identified significant results in this report

Low-Latency Sliding Window Algorithms for Formal Languages

Low-latency sliding window algorithms for regular and context-free languages are studied, where latency refers to the worst-case time spent for a single window update or query. For every regular language L it is shown that there exists a constant-latency solution that supports adding and removing symbols independently on both ends of the window (the so-called two-way variable-size model). We prove that this result extends to all visibly pushdown languages. For deterministic 1-counter languages we present a ?(log n) latency sliding window algorithm for the two-way variable-size model where n refers to the window size. We complement these results with a conditional lower bound: there exists a fixed real-time deterministic context-free language L such that, assuming the OMV (online matrix vector multiplication) conjecture, there is no sliding window algorithm for L with latency n^(1/2-?) for any ? > 0, even in the most restricted sliding window model (one-way fixed-size model). The above mentioned results all refer to the unit-cost RAM model with logarithmic word size. For regular languages we also present a refined picture using word sizes ?(1), ?(log log n), and ?(log n)

Image Display and Manipulation System (IDAMS) program documentation, Appendixes A-D

The IDAMS Processor is a package of task routines and support software that performs convolution filtering, image expansion, fast Fourier transformation, and other operations on a digital image tape. A unique task control card for that program, together with any necessary parameter cards, selects each processing technique to be applied to the input image. A variable number of tasks can be selected for execution by including the proper task and parameter cards in the input deck. An executive maintains control of the run; it initiates execution of each task in turn and handles any necessary error processing

ATAMM enhancement and multiprocessor performance evaluation

ATAMM (Algorithm To Architecture Mapping Model) enhancement and multiprocessor performance evaluation is discussed. The following topics are included: the ATAMM model; ATAMM enhancement; ADM (Advanced Development Model) implementation of ATAMM; and ATAMM support tools

On a block floating point implementation of an intrusion-detection algorithm

Call number: LD2668 .T4 1979 F63Master of Scienc

Development of algorithms for digital real time image processing on a DSP Processor

Rozpoznávanie tvárí je komplexný proces, ktorého hlavným ciežom je rozpoznanie žudskej tváre v obrázku alebo vo video sekvencii. Najčastejšími aplikáciami sú sledovacie a identifikačné systémy. Taktiež je rozpoznávanie tvárí dôležité vo výskume počítačového videnia a umelej inteligencií. Systémy rozpoznávania tvárí sú často založené na analýze obrazu alebo na neurónových sieťach. Táto práca sa zaoberá implementáciou algoritmu založeného na takzvaných „Eigenfaces“ tvárach. „Eigenfaces“ tváre sú výsledkom Analýzy hlavných komponent (Principal Component Analysis - PCA), ktorá extrahuje najdôležitejšie tvárové črty z originálneho obrázku. Táto metóda je založená na riešení lineárnej maticovej rovnice, kde zo známej kovariančnej matice sa počítajú takzvané „eigenvalues“ a „eigenvectors“, v preklade vlastné hodnoty a vlastné vektory. Tvár, ktorá má byť rozpoznaná, sa premietne do takzvaného „eigenspace“ (priestor vlastných hodnôt). Vlastné rozpoznanie je na základe porovnania takýchto tvárí s existujúcou databázou tvárí, ktorá je premietnutá do rovnakého „eigenspace“. Pred procesom rozpoznávania tvárí, musí byť tvár lokalizovaná v obrázku a upravená (normalizácia, kompenzácia svetelných podmienok a odstránenie šumu). Existuje mnoho algoritmov na lokalizáciu tváre, ale v tejto práci je použitý algoritmus lokalizácie tváre na základe farby žudskej pokožky, ktorý je rýchly a postačujúci pre túto aplikáciu. Algoritmy rozpoznávania tváre a lokalizácie tváre sú implementované do DSP procesoru Blackfin ADSP-BF561 od Analog Devices.Face recognition is a complex process that aims to recognize human faces in images or video sequences. Applications include surveillance and identification system, but face recognition is also invaluable in the research of computer vision and artificial intelligence. Face recognition systems are often based on either image analysis or neural networks. This work implements an algorithm based around the use of so-called eigenfaces. Eigenfaces are the result of a form of Principal Component Analysis (PCA), which extracts important facial features from the original image and is based on solving a linear matrix equation of the covariance matrix, eigenvalues and eigenvectors. A face that is to be recognized is thus projected onto the eigenspace; the results of that operation can be interpreted as the comparison of this face with an existing database of known faces. Before executing the actual recognition algorithm, faces need to be located inside the image and prepared (by doing normalization, lighting compensation and noise removal). Many algorithms exist, but this work uses a color based face detection algorithm, which is both fast and sufficient for this application. The face detection and recognition algorithms are implemented on a Blackfin ADSP-BF561 DSP processor from Analog Devices.