Real-time digital signal processing for new wavelength-to-the-user optical access networks

Nowadays, optical access networks provide high capacity to end users with growing availability of multimedia contents that can be streamed to fixed or mobile devices. In this regard, one of the most flexible and low-cost approaches is Passive Optical Network (PON) that is used in Fiber-to-the-Home (FTTH). Due to the growing of the bandwidth demands, Wavelength Division Multiplexing (WDM), and later on ultra-dense WDM (udWDM) PON, with a narrow channel spacing, to increase the number of users through a single fiber, has been deployed. The udWDM-PON with coherent technology is an attractive solution for the next generation optical access networks with advanced digital signal processing (DSP). Thanks to the higher sensitivity and improved channel selectivity in coherent detection with efficient DSP, optical networks support larger number of users in longer distances. Since the cost is the main concern in the optical access networks, this thesis presents DSP architectures in coherent receiver (Rx), based on low-cost direct phase modulated commercial DFB lasers. The proposals are completely in agreement with consept of wavelength-to-the-user, where each client in optical network is dedicated to an individual wavelength. Next, in a 6.25 GHz spaced udWDM grid with the optimized DSP techniques and phase-shift-keying (PSK) modulation format, the high sensitivity is achieved in real-time field-programmable-gate-array (FPGA) implementations. Moreover, this thesis reduces hardware complexity of optical carrier recovery (CR) with two various strategies. First, based on differential mth-power frequency estimator (FE) by using look-up-tables (LUTs) and second, LUT-free CR architecture, with optimizing the power consumption and hardware resources, as well as improving the channel selectivity in terms of speed and robustness. Furthermore, by designing very simple but efficient clock recovery, a symbol-rate DSP architecture, which process data using only one sample per symbol (1-sps), for polarization diversity (POD) structure, becomes possible. It makes the DSP independent from state-of-polarization (SOP), even in the case of low-cost optical front-end and low-speed analog-to-digital converters (ADCs), keeps the performance high as well as sensitivity in real-time implementations on FPGA.Avui en dia, les xarxes d'accés òptic proporcionen una alta capacitat als usuaris finals amb una creixent disponibilitat de continguts multimèdia que es poden transmetre a dispositius fixos o mòbils. En aquest sentit, un dels enfocaments més flexibles i de baix cost és la Xarxa Òptica Passiva (PON) que s'utilitza a Fibra-fins-la-Llar (FTTH). A causa del creixent requeriment de l'ample de banda, s'ha desplegat la multiplexació de divisió d'ona (WDM) i, posteriorment, el PON amb WDM d'alta densitat (udWDM), amb un espaiat estret de canals, per augmentar el nombre d'usuaris a través d'una sola fibra. L'udWDM-PON amb tecnologia coherent és una solució atractiva per a les xarxes d'accés òptic d'última generació amb processament avançat de senyal digital (DSP). Gràcies a la major sensibilitat i a la selectivitat millorada del canal en la detecció coherent amb DSP eficient, les xarxes òptiques suporten un nombre més gran d'usuaris a distàncies més llargues. Atès que el cost és la principal preocupació en les xarxes d'accés òptic, aquesta tesi presenta arquitectures DSP en receptor coherent (Rx), basades en làsers DFB comercials modulats en fase directa de baix cost. Les propostes estan d'acord amb la asignació de la longitud d'ona a l'usuari, on a cada client de la xarxa òptica se li dedica a una longitud d'ona individual. A continuació, en una graella udWDM espaciada de 6,25 GHz amb les tècniques de DSP optimitzades i el format de modulació de fase (PSK), s'aconsegueix l'alta sensibilitat en implementacions field-programable-gate-array (FPGA) en temps real. A més, aquesta tesi redueix la complexitat del maquinari de recuperació òptica de portadors (CR) amb dues estratègies diverses. Primer, basat en un estimador de freqüència de potència diferencial (FE) mitjançant l'ús de taules de cerca (LUTs) i, en segon lloc, l'arquitectura CR sense LUT, amb l'optimització del consum d'energia i els recursos de maquinari, a més de millorar la selectivitat del canal en termes de velocitat i robustesa. A més, al dissenyar una recuperació de rellotge molt simple, però eficaç, es fa possible una arquitectura DSP a la velocitat dels símbols, que processa dades utilitzant només una mostra per símbol (1-sps) per a l'estructura de la diversitat de polarització òptica (POD). Fa que el DSP sigui independent de l'estat de polarització (SOP), fins i tot en el cas dels analog-to-digital converters (ADC) de front-end òptics de baix cost, i manté el rendiment alt i la sensibilitat en les implementacions en temps real de FPGA

Real-time digital signal processing for new wavelength-to-the-user optical access networks

Nowadays, optical access networks provide high capacity to end users with growing availability of multimedia contents that can be streamed to fixed or mobile devices. In this regard, one of the most flexible and low-cost approaches is Passive Optical Network (PON) that is used in Fiber-to-the-Home (FTTH). Due to the growing of the bandwidth demands, Wavelength Division Multiplexing (WDM), and later on ultra-dense WDM (udWDM) PON, with a narrow channel spacing, to increase the number of users through a single fiber, has been deployed. The udWDM-PON with coherent technology is an attractive solution for the next generation optical access networks with advanced digital signal processing (DSP). Thanks to the higher sensitivity and improved channel selectivity in coherent detection with efficient DSP, optical networks support larger number of users in longer distances. Since the cost is the main concern in the optical access networks, this thesis presents DSP architectures in coherent receiver (Rx), based on low-cost direct phase modulated commercial DFB lasers. The proposals are completely in agreement with consept of wavelength-to-the-user, where each client in optical network is dedicated to an individual wavelength. Next, in a 6.25 GHz spaced udWDM grid with the optimized DSP techniques and phase-shift-keying (PSK) modulation format, the high sensitivity is achieved in real-time field-programmable-gate-array (FPGA) implementations. Moreover, this thesis reduces hardware complexity of optical carrier recovery (CR) with two various strategies. First, based on differential mth-power frequency estimator (FE) by using look-up-tables (LUTs) and second, LUT-free CR architecture, with optimizing the power consumption and hardware resources, as well as improving the channel selectivity in terms of speed and robustness. Furthermore, by designing very simple but efficient clock recovery, a symbol-rate DSP architecture, which process data using only one sample per symbol (1-sps), for polarization diversity (POD) structure, becomes possible. It makes the DSP independent from state-of-polarization (SOP), even in the case of low-cost optical front-end and low-speed analog-to-digital converters (ADCs), keeps the performance high as well as sensitivity in real-time implementations on FPGA.Avui en dia, les xarxes d'accés òptic proporcionen una alta capacitat als usuaris finals amb una creixent disponibilitat de continguts multimèdia que es poden transmetre a dispositius fixos o mòbils. En aquest sentit, un dels enfocaments més flexibles i de baix cost és la Xarxa Òptica Passiva (PON) que s'utilitza a Fibra-fins-la-Llar (FTTH). A causa del creixent requeriment de l'ample de banda, s'ha desplegat la multiplexació de divisió d'ona (WDM) i, posteriorment, el PON amb WDM d'alta densitat (udWDM), amb un espaiat estret de canals, per augmentar el nombre d'usuaris a través d'una sola fibra. L'udWDM-PON amb tecnologia coherent és una solució atractiva per a les xarxes d'accés òptic d'última generació amb processament avançat de senyal digital (DSP). Gràcies a la major sensibilitat i a la selectivitat millorada del canal en la detecció coherent amb DSP eficient, les xarxes òptiques suporten un nombre més gran d'usuaris a distàncies més llargues. Atès que el cost és la principal preocupació en les xarxes d'accés òptic, aquesta tesi presenta arquitectures DSP en receptor coherent (Rx), basades en làsers DFB comercials modulats en fase directa de baix cost. Les propostes estan d'acord amb la asignació de la longitud d'ona a l'usuari, on a cada client de la xarxa òptica se li dedica a una longitud d'ona individual. A continuació, en una graella udWDM espaciada de 6,25 GHz amb les tècniques de DSP optimitzades i el format de modulació de fase (PSK), s'aconsegueix l'alta sensibilitat en implementacions field-programable-gate-array (FPGA) en temps real. A més, aquesta tesi redueix la complexitat del maquinari de recuperació òptica de portadors (CR) amb dues estratègies diverses. Primer, basat en un estimador de freqüència de potència diferencial (FE) mitjançant l'ús de taules de cerca (LUTs) i, en segon lloc, l'arquitectura CR sense LUT, amb l'optimització del consum d'energia i els recursos de maquinari, a més de millorar la selectivitat del canal en termes de velocitat i robustesa. A més, al dissenyar una recuperació de rellotge molt simple, però eficaç, es fa possible una arquitectura DSP a la velocitat dels símbols, que processa dades utilitzant només una mostra per símbol (1-sps) per a l'estructura de la diversitat de polarització òptica (POD). Fa que el DSP sigui independent de l'estat de polarització (SOP), fins i tot en el cas dels analog-to-digital converters (ADC) de front-end òptics de baix cost, i manté el rendiment alt i la sensibilitat en les implementacions en temps real de FPGA.Postprint (published version

Utilizing digital design techniques and circuits to improve energy and design efficiency of analog and mixed-signal circuits

Technology scaling has long driven large growth in the electronics market. With each successive technology generation, digital circuits become more power and area efficient. The large performance increases realized for digital circuits due to digital scaling have not translated to similar performance improvements for analog circuits. First, noise-limited analog circuits are not capable of leveraging the reduced parasitics of advanced processes, since capacitor sizes are generally set by noise requirements. Second, analog circuit performance is closely tied to the achievable device intrinsic gain, which degrades as process sizes shrink. Reduced supply voltages further exacerbate this issue, as the achievable gain per stage is limited by the number of devices that can be stacked while maintaining all devices in saturation. Finally, process variation increases with decreased feature sizes, so analog circuits have deal with increased mismatch and wider variations in threshold voltages, increasing the time required to design a circuit that is robust across process, voltage, and temperature (PVT) variation. This work seeks to address the limitations of analog circuits in advanced technologies by leveraging digital techniques and digital-like circuits that offer improved scalability. The first half of this dissertation investigates replacing the traditional closed-loop residue amplifier in a pipeline analog-to-digital converter (ADC) with an open loop dynamic amplifier. Previous works incorporating dynamic amplifiers have struggled to achieve large gains and have suffered from offset mismatch between the comparator and amplifier, which will only get worse in more advanced technologies. We propose the usage of a residue amplifier that combines an integration stage, to ensure low noise operation, with a positive feedback stage, to ensure high gain and high speed operation. By utilizing this topology, the proposed amplifier was the first dynamic amplifier to achieve a high gain of 32. Additionally, the proposed amplifier can reuse existing comparator hardware in the ADC, removing all offset mismatch between comparator and amplifier. Digital calibration techniques were applied to ensure a constant gain across PVT. The next part of this dissertation tries to overcome the scaling challenges for noise-limited ADCs with band-limited input signals. By leveraging digital filtering techniques to generate a prediction of the band-limited signal, the conversion can be limited to a range that is a fraction of the total ADC input range, allowing for significant decreases in reference and comparator power consumption. This work extends previous works by enabling accurate predictions for any band-limited signal characteristic. Previous works only focused on accurate predictions for low-activity signals. Finally, the large compute power enabled by modern technology scaling is leveraged to improve the design efficiency of analog circuits. A new automated circuit sizing tool is proposed that can achieve better performance than manual designs done by experts in a much shorter amount of time. All of these techniques help to alleviate the power and design efficiency limitations caused by technology scaling.Electrical and Computer Engineerin

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

Observer techniques for estimating the state-of-charge and state-of-health of VRLABs for hybrid electric vehicles

The paper describes the application of observer-based state-estimation techniques for the real-time prediction of state-of-charge (SoC) and state-of-health (SoH) of lead-acid cells. Specifically, an approach based on the well-known Kalman filter, is employed, to estimate SoC, and the subsequent use of the EKF to accommodate model non-linearities to predict battery SoH. The underlying dynamic behaviour of each cell is based on a generic Randles' equivalent circuit comprising of two-capacitors (bulk and surface) and three resistors, (terminal, transfer and self-discharging). The presented techniques are shown to correct for offset, drift and long-term state divergence-an unfortunate feature of employing stand-alone models and more traditional coulomb-counting techniques. Measurements using real-time road data are used to compare the performance of conventional integration-based methods for estimating SoC, with those predicted from the presented state estimation schemes. Results show that the proposed methodologies are superior with SoC being estimated to be within 1% of measured. Moreover, by accounting for the nonlinearities present within the dynamic cell model, the application of an EKF is shown to provide verifiable indications of SoH of the cell pack

The Fluorescence Detector of the Pierre Auger Observatory

The Pierre Auger Observatory is a hybrid detector for ultra-high energy cosmic rays. It combines a surface array to measure secondary particles at ground level together with a fluorescence detector to measure the development of air showers in the atmosphere above the array. The fluorescence detector comprises 24 large telescopes specialized for measuring the nitrogen fluorescence caused by charged particles of cosmic ray air showers. In this paper we describe the components of the fluorescence detector including its optical system, the design of the camera, the electronics, and the systems for relative and absolute calibration. We also discuss the operation and the monitoring of the detector. Finally, we evaluate the detector performance and precision of shower reconstructions.Comment: 53 pages. Submitted to Nuclear Instruments and Methods in Physics Research Section

Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs

During the past decade, SAR ADCs have enjoyed increasing prominence due to their inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power consumption, mitigating thermal noise, and improving bandwidth, however most of those that use non-hybrid architectures are limited to moderate (8-10 bit) resolu- tion. Assuming an almost rail-to-rail dynamic range, comparator noise and DAC element mismatch constraints are critical but not insurmountable at 10 bits of resolution or less in sub-100nm processes. On the other hand, analysis shows that for medium-resolution ADCs (11-15 bits, depending on the LSB voltage of the converter), the mismatch sizing constraint still dominates unit capacitor sizing over the kT/C sampling noise constraint, and can only be mitigated by drawing increasingly larger capacitors. The focus of this work is to extend the scaling benefits of the SAR architecture to medium and higher ADC resolutions through mitigating and ultimately harnessing DAC element mismatch. This goal is achieved via a novel, completely reconfigurable capacitor DAC that allows the rearranging of capacitors to different trial groupings in the SAR cycle so that mismatch can be canceled. The DAC is implemented in a 12-bit SAR ADC in 65nm CMOS, and a nearly 2-bit improvement in linearity is demonstrated with a simple reconfiguration algorithm.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138630/1/ncolins_1.pd