Systems-on-Chip (SoC) for applications in High-Energy Physics

In view of the Time Projection Chamber for the future Linear Collider (LCTPC), a new front-end Application-Specific Integrated Circuit has been developed: the 16 channels Super-Altro Demonstrator. Given the small pad area of 1mm x 4mm, the chip is a compact integrated system, including signal preamplification/shaping, 10-bit analog-to-digital conversion and digital signal processing. Adequate design techniques were used to reduce noise coupling between analog and digital parts of the system. The bunch train structure of the linear collider is exploited by the introduction of power pulsing features in the design, which result in a significant reduction of the power consumption. The tests carried out show noise as low as 316 electrons and effectiveness of the power pulsing approach. Super-Altro can be used for studies of gaseous detector readout with classical wire chambers as well as modern GEMs and MicroMegas. This thesis also studies Analog-to-Digital Converters (ADC) suitable for integration in High-Energy Physics front-end systems. Simulations show the feasibility of a 12-bit 100MHz pipeline ADC in a 130nm CMOS technology

Voltage and Time-Domain Analog Circuit Techniques for Scaled CMOS Technologies

CMOS technology scaling has resulted in reduced supply voltage and intrinsic voltage gain of the transistor. This presents challenges to the analog circuit designers due to lower signal swing and achievable signal to noise ratio (SNR), leading to increased power consumption. At the same time, device speed has increased in lower design nodes, which has not been directly beneficial for analog circuit design. This thesis presents voltage-domain and time-domain circuit scaling friendly circuit architectures that minimize the power consumption and benefit from the increasing transistor speeds. In the voltage-domain, an on-the-fly gain selection block is demonstrated as an alternative to the traditional MDAC architecture to enhance the input dynamic range of a medium-resolution medium-speed analog-to-digital converter (ADC) at reduced supply voltages. The proposed design also eliminates the need for a reference buffer, thus providing power savings. The measured prototype enhances the input dynamic range of a 12bit, 40MSPS ADC to 80.6dB at 1.2V supply voltage. In the time-domain, a generic circuit design approach is presented, followed by an in-depth analysis of Voltage-Controlled-Oscillator based Operational Transconductance Amplifiers (VCO-OTAs). A discrete-time-domain small-signal model based on the zero crossings of the internal VCOs is developed to predict the stability, the step response, and the frequency response of the circuit when placed in feedback. The model accurately predicts the circuit behavior for an arbitrary input frequency, even as the VCO free-running frequency approaches the unity-gain bandwidth of the closed-loop system, where other intuitive small-signal models available in the literature fail. Next, we present an application of VCO-OTA in designing a baseband trans-impedance amplifier (TIA) for current-mode receivers as a scaling-friendly and power-efficient alternative to the inverter-based OTA. We illustrate a design methodology for the choice of the VCO-OTA parameters in the context of a receiver design with an example of a 20MHz RF-channel-bandwidth receiver operating at 2GHz. Receiver simulation results demonstrate an improvement of up to 12dB in blocker 1dB compression point (B1dB) for slightly higher power consumption or up to 2.6x power reduction of the TIA resulting in up to 2x power reduction of the receiver for similar B1dB performance. Next, we present some examples of VCO-OTAs. We first illustrate the benefit of a VCO-OTA in a low-dropout-voltage regulator to achieve a dropout voltage of only100mV and operating down to 0.8V input supply, compared to the prototype based on traditional OTA with a minimum dropout voltage of 150mV, operating at a minimum of 1.2V supply. Both the capacitor-less prototypes can drive up to 1nF load capacitor and provide a current of 60mA. The next prototype showcases a method to reduce the power consumption of a VCO-OTA and spurs at the VCO frequency, with an application in the design of a fourth-order Butterworth filter at 4MHz. The thesis concludes with a design example of 0.2V VCO-OTA

Design of high speed folding and interpolating analog-to-digital converter

High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F&I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F&I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F&I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35μm CMOS process to verify the ideas. The S/H and F&I ADC prototype is realized in 0.35μm double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

An 18GHz Wide-Band Buffer

Recent developments in wireless communication and systems, such as sixth-generation (6G), radar and instrumentation have led to massive use of high-frequency carriers. As a result, there is a high demand for Analog-to-Digital Converters (ADCs) in direct-conversion architectures with high bandwidth, high-resolution, and with the highest possible power efficiency and spectral purity. A potential performance enhancement of an ADC can be realized by adding a voltage Input Buffer (IB). To increase the IB bandwidth and decrease the distortion from the nonlinear sampling circuit, a low output impedance is required. Therefore, to achieve low output impedance, it is necessary to dissipate power that is often equal to or greater than the power dissipated in the rest of the ADC blocks combined, since the output impedance is inversely proportional to the bias current. Consequently, input buffers are one of the most "power-hungry" building blocks of any direct receiver chain. In recent years, due to the high ADC resolution and quantization range, the existing approaches use IBs with supply voltages above the nominal rails, for instance, 2.5 or 4.0 V, to increase the linearity and to not limit the ADC output swing. However, it inherently creates reliability and robustness issues. This work investigates several different input buffers implemented in 7 nm FinFET technology with 1.8V of supply voltage in which a one pico farad of sampling capacitance is driven. The study starts by exploring four single-stage topologies in thick gate devices with and without linearity techniques, for example, the drain-source voltage "bootstrap" technique. Moreover, two bandwidth extension techniques are introduced, for instance, the Bridge T-coil with Series Peaking and the Distributed Approach. Lastly, two-stage IB architectures with thick oxide devices together with thin oxide devices are implemented. Finally, the new solutions presented meet the requirements by exhibiting more than 18 GHz of bandwidth with a linearity (IIP3) higher than 16.3 dBm, and a DC power consumption lower than 178.2 mW without compromising reliability and robustness issues.Os mais recentes desenvolvimentos nos sistemas de comunicação sem fios, como a sexta geração (6G) de redes móveis, levaram ao uso massivo de portadoras de alta frequência. Com efeito, é crescente a demanda por conversores analógico-digital (ADCs) nas arquiteturas de conversão direta, com elevada largura de banda, de alta resolução, com um baixo consumo de energia e com uma elevada linearidade. Uma potencial melhoria no desempenho do ADC pode ser alcançada através de um input buffer (IB). Para aumentar a largura de banda do IB e diminuir a distorção causada pelo circuito de amostragem é necessária uma baixa impedância de saída. Sendo a impedância de saída inversamente proporcional à corrente de polarização, para alcançar umaimpedância de saída baixa é essencial dissiparpotência que muitas das vezes é igualou superior à soma da potência consumida no resto dos blocos do ADC. Consequentemente, o input buffer é um dos blocos da cadeia recetora que mais energia consume. Nos últimos anos, devido à elevada resolução do ADC, as abordagens existentes usam input buffers com tensões de alimentação superiores à tensão nominal de alimentação, por exemplo, 2.5 ou 4.0 V, de forma a aumentar a linearidade e não limitar a tensão saída do ADC. Porém, inerentemente surgem questões de fiabilidade e robustez. Neste contexto, o escopo do presente trabalho é investigar diversos input buffers implementados em tecnologia 7 nm FinFET com 1.8V de tensão de alimentação e com uma capacidade de carga de um pico farad. O estudo começa por explorar quatro topologias de input buffer com dispositivos de grandes dimensões, com e sem técnicas de linearidade, nomeadamente, a técnica que força a tensão dreno-fonte a ser constante. Ademais, são introduzidas duas técnicas que aumentam a largura de banda, The Bridge T-coil com Series Peaking e a Distributed Approach. Finalmente, são implementadas arquiteturas de input buffer com dois andares em dispositivos de pequenas e grandes dimensões. Por último, são apresentadas novas soluções que cumprem inteiramente as especificações, uma vez que exibem uma largura de banda maior que 18 GHz com uma linearidade (IIP3) superior 16.3 dBm e um consumo de potência inferior a 178.2mW, sem comprometer a fiabilidade e a robustez dos dispositivos

Efficient Continuous-Time Sigma-Delta Converters for High Frequency Applications

Over the years Continuous-Time (CT) Sigma-Delta (ΣΔ) modulators have received a lot of attention due to their ability to efficiently digitize a variety of signals, and suitability for many different applications. Because of their tolerance to component mismatch, the easy to drive input structure, as well as intrinsic anti-aliasing filtering and noise shaping abilities, CTΣΔ modulators have become one of the most popular data-converter type for high dynamic range and moderate/wide bandwidth. This trend is the result of faster CMOS technologies along with design innovations such as better architectures and faster amplifiers. In other words, CTΣΔ modulators are starting to offer the best of both worlds, with high resolution and high bandwidth. This dissertation focuses on the bandwidth and resolution of CTΣΔ modulators. The goal of this research is to use the noise shaping benefits of CTΣΔ modulators for different wireless applications, while achieving high resolution and/or wide bandwidth. For this purpose, this research focuses on two different application areas that demand speed and resolution. These are a low-noise high-resolution time-to-digital converter (TDC), ideal for digital phase lock loops (PLL), and a very high-speed, wide-bandwidth CTΣΔ modulator for wireless communication. The first part of this dissertation presents a new noise shaping time-to-digital converter, based on a CTΣΔ modulator. This is intended to reduce the in-band phase noise of a high frequency digital phase lock loop (PLL) without reducing its loop bandwidth. To prove the effectiveness of the proposed TDC, 30GHz and a 40GHz fractional-N digital PLL are designed as a signal sources for a 240GHz FMCW radar system. Both prototypes are fabricated in a 65nm CMOS process. The standalone TDC achieves 81dB dynamic range and 13.2 equivalent number of bits (ENOB) with 176fs integrated-rms noise from 1MHz bandwidth. The in-band phase noise of the 30GHz digital fractional-N PLL is measured as -87dBc/Hz at a 100kHz offset which is equivalent to -212.6dBc/Hz2 normalized in-band phase noise. The second part of this dissertation focuses on high-speed (GS/s) CTΣΔ modulators for wireless communication, and introduces a new time-interleaved reference data weighted averaging (TI-RDWA) architecture suitable for GS/s CTΣΔ modulators. This new architecture shapes the digital-to-analog converter (DAC) mismatch effects in a CTΣΔ modulator at GS/s operating speeds. It allows us to use smaller DAC unit sizes to reduce area and power consumption for the same bandwidth. The prototype 5GS/s CTΣΔ modulator with TI-RDWA is fabricated in 40nm CMOS and it achieves 156MHz bandwidth, 70dB dynamic range, 84dB SFDR and a Schreier FoM of 158.3dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138763/1/bdayanik_1.pd

Energy and area efficient techniques for data converters

Data converters are ubiquitous building blocks of a signal chain. The rapid increase in communication and connectivity devices presents new avenues for pushing the state of the art analog to digital converters. Techniques for improving resolution, bandwidth, linearity and bit-error rate, while reducing the power, energy and area is the motivation for this research. This research focuses on achieving this goal by enabling circuit techniques, architecture techniques and calibration methods. The following techniques are proposed for enabling power, area and energy efficient analog to digital converter techniques. 1. A capacitor switching scheme for successive approximation ADC is introduced to enable 93.4% energy reduction and 75 % reduction in capacitor area as compared to a conventional SAR ADCs. 2. Asynchronous correlated level shifting technique for improving current source linearity and power supply rejection ratio of zero crossing based circuits is proposed. This technique enables asynchronous ADC architectures for energy efficient system. 3. Unified gain enhancement model is proposed to catalogue gain enhancement techniques. Class-A+ and Replicated Parallel Gain Enhancement (RPGe) amplifiers are introduced as parallel gain enhancement techniques for switched capacitor circuits. A prototype pipelined ADC using RPGE amplifier achieves 74.9 dB SNDR, 90.8 dB SFDR, 87 dB THD at 20 MS/s. Built in 1P4M 0.18 μm technology and operating at 1.3 V supply, the ADC consumes 5.9 mW. The ADC occupies 3.06 sq. mm and has a figure of merit of 65 fJ /conversion step. Extracted simulation results of the prototype pipeline ADC using dynamic RPGE amplifier achieve 74 dB SNDR, 90 dB SFDR, and 85 dB THD at 30 MS /s in a 0.18 μm process. The ADC consumes 6.6 mW from a 1.3 V supply and achieves a figure of merit of 40 fJ/C-S. 4. A low-gain amplifier based V-T converter is utilized along with a TDC to replace the function of flash ADC and the DAC references in a pipeline ADC. The simulated/ extracted performance of the chip is 12bit, 100 MHz in 65nm process while consuming approximately 8-9 mA from 1 V supply. 5. A measurement technique for detecting and correcting bit-error rate in ADCs is proposed. This multi-path ADC technique squares the bit-error rate of the ADC without consuming additional analog power. The area increase is negligible compared to the conventional modular redundancy techniques. This technique can be applied to digitally detect and correct single event transients for ADCs. A three-path ADC can restore the ADC performance independent of the input frequency and number of errors in a single path. 6. LMS algorithm is used to estimate the VCO non-linearity by using the VCO as a Nyquist ADC and utilizing a slow but accurate ADC. The simulated ADC performance improves from 5 bits to 7.8 bits by using a second order fit to the VCO non-linearity

Design techniques for low noise and high speed A/D converters

Analog-to-digital (A/D) conversion is a process that bridges the real analog world to digital signal processing. It takes a continuous-time, continuous amplitude signal as its input and outputs a discrete-time, discrete-amplitude signal. The resolution and sampling rate of an A/D converter vary depending on the application. Recently, there has been a growing demand for broadband (>1 MHz), high-resolution (>14bits) A/D converters. Applications that demand such converters include asymmetric digital subscriber line (ADSL) modems, cellular systems, high accuracy instrumentation, and medical imaging systems. This thesis suggests some design techniques for such high resolution and high sampling rate A/D converters. As the A/D converter performance keeps on increasing it becomes increasingly difficult for the input driver to settle to required accuracy within the sampling time. This is because of the use of larger sampling capacitor (increased resolution) and a decrease in sampling time (higher speed). So there is an increasing trend to have a driver integrated onchip along with A/D converter. The first contribution of this thesis is to present a new precharge scheme which enables integrating the input buffer with A/D converter in standard CMOS process. The buffer also uses a novel multi-path common mode feedback scheme to stabilize the common mode loop at high speeds. Another major problem in achieving very high Signal to Noise and Distortion Ratio (SNDR) is the capacitor mismatch in Digital to Analog Converters (DAC) inherent in the A/D converters. The mismatch between the capacitor causes harmonic distortion, which may not be acceptable. The analysis of Dynamic Element Matching (DEM) technique as applicable to broadband data-converters is presented and a novel second order notch-DEM is introduced. In this thesis we present a method to calibrate the DAC. We also show that a combination of digital error correction and dynamic element matching is optimal in terms of test time or calibration time. Even if we are using dynamic element matching techniques, it is still critical to get the best matching of unit elements possible in a given technology. The matching obtained may be limited either by random variations in the unit capacitor or by gradient effects. In this thesis we present layout techniques for capacitor arrays, and the matching results obtained in measurement from a test-chip are presented. Thus we present various design techniques for high speed and low noise A/D converters in this thesis. The techniques described are quite general and can be applied to most of the types of A/D converters

Frontend em tempo real para cognitive radio inspirado na cóclea humana

Mestrado em Engenharia Electrónica e TelecomunicaçõesNesta tese vamos discutir a implementação e desenvolvimento de um frontend inspirado na cóclea humana que é capaz de amostrar sinais RF com uma larga largura de banda e gama dinâmica. Este front-end usa um multiplexer de RF de 8 canais amostrado por uma placa com 8 ADCs a funcionar a 250MSPS. Uma placa de desenvolvimento com uma FPGA controla a ADC e implementa os ltros de síntese digitais e liga a um computador pessoal para transferir toda a informação e mudar os coe cientes dos ltros em tempo real.In this thesis it will be discussed the real time implementation and development of a front-end inspired by the Human Cochlea that is able to sample RF signals with a large bandwidth and dynamic range. This front-end uses an 8 channel RF multiplexer sampled by an 8 channel 250MSPS ADC board. A FPGA board controls the ADC, implements the digital synthesis lter bank and connects to a personal computer to transfer the data and to change the lters in real-time

Energy Harvesting for Self-Powered Wireless Sensors

A wireless sensor system is proposed for a targeted deployment in civil infrastructures (namely bridges) to help mitigate the growing problem of deterioration of civil infrastructures. The sensor motes are self-powered via a novel magnetic shape memory alloy (MSMA) energy harvesting material and a low-frequency, low-power rectifier multiplier (RM). Experimental characterizations of the MSMA device and the RM are presented. A study on practical implementation of a strain gauge sensor and its application in the proposed sensor system are undertaken and a low-power successive approximation register analog-to-digital converter (SAR ADC) is presented. The SAR ADC was fabricated and laboratory characterizations show the proposed low-voltage topology is a viable candidate for deployment in the proposed sensor system. Additionally, a wireless transmitter is proposed to transmit the SAR ADC output using on-off keying (OOK) modulation with an impulse radio ultra-wideband (IR-UWB) transmitter (TX). The RM and SAR ADC were fabricated in ON 0.5 micrometer CMOS process. An alternative transmitter architecture is also presented for use in the 3-10GHz UWB band. Unlike the IR-UWB TX described for the proposed wireless sensor system, the presented transmitter is designed to transfer large amounts of information with little concern for power consumption. This second method of data transmission divides the 3-10GHz spectrum into 528MHz sub-bands and "hops" between these sub-bands during data transmission. The data is sent over these multiple channels for short distances (?3-10m) at data rates over a few hundred million bits per second (Mbps). An UWB TX is presented for implementation in mode-I (3.1-4.6GHz) UWB which utilizes multi-band orthogonal frequency division multiplexing (MB-OFDM) to encode the information. The TX was designed and fabricated using UMC 0.13 micrometer CMOS technology. Measurement results and theoretical system level budgeting are presented for the proposed UWB TX