Design of 5v Digital Standard Cells And I/O Libraries for Military Standard Temperatures

The scope of this research work is to develop digital standard cell and I/O cell libraries operable at 5V power supply and operable up to 125�C using Peregrine 0.5um 3.3 V process. Device geometries are selected based on Ion/Ioff ratios at 125�C. The cell schematic, layout and abstracted views are generated for both the libraries The Standard cell and I/O libraries are characterized for timing and power and the characterization data is realized in various formats compatible with logic synthesis and place and route tools. The pads have been tested for robustness to ESD. A tutorial on abstraction of standard cells and IO cells is prepared using the Cadence Abstract Generator.School of Electrical & Computer Engineerin

Understanding, modeling, and mitigating system-level ESD in integrated circuits

This dissertation describes several studies regarding the effects of system-level electrostatic discharge (ESD) and how to model and mitigate them. The topics in this dissertation fall into two broad categories: modeling pieces of a system-level ESD test setup and phenomenological studies. Simulation is an important tool for achieving quality designs quickly. However, modeling methodologies for system-level ESD are not yet mature. This dissertation aims to improve (i) simulation models of ESD protection elements, (ii) simulation models of ESD guns, and (iii) analytic models of rail-clamp circuits used for power-on ESD protection. Simulation models for two common ESD protection elements, diodes and silicon controlled rectifiers (SCR) are presented and evaluated, specifically with regard to the origins of poor voltage clamping. These models can be used for ESD network design and simulation; their applicability is not limited only to system-level ESD. Next, a circuit simulation model for an ESD gun (used to produce system-level ESD stresses) is presented. This model can be used for trouble-shooting and design. Lastly, an analytic model of rail-clamp circuits during system-level ESD is presented. These circuits can produce unstable oscillations or ringing on the supply; such problems must be eliminated during design. Analytic models help the designer understand how circuit parameters will impact the circuit’s performance. System-level ESD is a relatively new requirement being imposed on IC manufacturers; as such, current understanding of how system-level ESD affects ICs is not yet mature. This dissertation includes two studies that expand upon this knowledge. The first demonstrates that ground bounce due system-level ESD stress can lead to severe problems, including latch-up and power integrity problems. The second reports observations regarding input noise signals at an IC pin during system-level ESD stress. Lastly, this dissertation discusses experimental design of a test chip that will be manufactured shortly after this dissertation is completed. These experiments focus on observing and suppressing various errors that can occur during system-level ESD, arising from both noise at the inputs and power fluctuations. Additionally, this test chip includes standalone test structures that are used to reproduce power supply problems predicted in other sections of this dissertation

Integrated Circuit Design for Miniaturized, Trackable, Ultrasound Based Biomedical Implants

This thesis focuses on the design of an ultrasonography compatible implantable sensor platform, as a novel approach that implements a miniaturized, battery-less, real-time trackable parallel biosensing system. In addition to the frontend circuit, a sub-nW fully integrated pH sensor is designed in a way that can be easily integrated with the proposed sonography-compatible sensor platform. Combining the two integrated circuits together, the whole system will be able to map in vivo physiological information acquired from a distributed set of sensors on top of the ultrasound movie, leading to the idea envisioned as “augmented ultrasonography”. Implemented in a 0.18 μm technology, an ultrasound power and data frontend circuit is designed to enable medical sensing implants to operate in an ultrasonography compatible way. When placed within the field of view of an imaging transducer, the frontend circuit harvests the power through a piece of piezo crystal from a minimally modified brightness-mode (B-mode) ultrasound imaging process that is commonly adopted in modern medical practices. The implant can also establish bi-directional data communication channels with the imaging transducer, allowing data to be transmitted in a way synchronized to the frame rate of the B-mode film. The design of the circuit is made possible by a combination of ultra-low-power circuit techniques and novel frontend circuit topologies, as imaging ultrasound waves in the form of short pulses with extremely low duty cycle poses challenges that has not previously seen in other implantable sensor systems. The proposed prototype achieves a total area of 0.6mm² for the integrated circuit (IC), as well as 71mm theoretical maximum implantable depth (up to 40 mm is verified experimentally). These two together give opportunities for this design to become the next generation solution for deep-tissue bio-sensing implants. Realized using the same 0.18 μm technology, the fully integrated pH sensor is designed to deliver accurate pH readouts, at a reasonable speed of 1 sample per second, while consuming only 0.72 nW of power. Using an ion-sensitive field effect transistor (ISFET) and reference field effect transistor pair (REFET), the IC requires minimum additional post fabrication to deliver 10-bit resolution pH readouts at an end-to-end sensitivity of 65.8 LSB/pH. When working as a standalone device, this work advances the state-of-the-art of ISFET based pH sensor design. With an addition of 0.46 mm² of area, it is possible to integrate it with the ultrasound sonography compatible implant platform. This potential integration will further advance the vision of the augmented ultrasonography: real-time display of physiological information in a B-mode film, with the help from a distributed bio-sensor system for deep-tissue physiology monitoring

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

Analog and mixed-signal circuitry for system-assisted high-speed I/O links

The state-of-the-art design methodology for high-speed I/O links is to specify component-level design requirements to achieve high-fidelity component-level performance. While designing each component in the link with high fidelity guarantees a reliable link, it does not inherently optimize the link for metrics such as the power, design complexity, or bit error rate performance. Recently, due to the increased demand for data bandwidth in backplane I/O, a system-assisted design methodology has been developed to optimize the system for a given set of metrics. By optimizing on the system level rather than the component level, the performance at the component level can be reduced from high quality to sufficient when the component is deployed within the I/O link. The new system-level design methodology encourages the utilization of novel circuit architectures. In this dissertation, novel analog and mixed-signal circuitry for system-assisted high-speed I/O links is presented. The novel circuitry expands upon traditional analog and mixed-signal circuit architectures in order to achieve system-level design goals and requirements without significant power or area overhead

A Sub-nW 2.4 GHz Transmitter for Low Data-Rate Sensing Applications

This paper presents the design of a narrowband transmitter and antenna system that achieves an average power consumption of 78 pW when operating at a duty-cycled data rate of 1 bps. Fabricated in a 0.18 μm CMOS process, the transmitter employs a direct-RF power oscillator topology where a loop antenna acts as a both a radiative and resonant element. The low-complexity single-stage architecture, in combination with aggressive power gating techniques and sizing optimizations, limited the standby power of the transmitter to only 39.7 pW at 0.8 V. Supporting both OOK and FSK modulations at 2.4 GHz, the transmitter consumed as low as 38 pJ/bit at an active-mode data rate of 5 Mbps. The loop antenna and integrated diodes were also used as part of a wireless power transfer receiver in order to kick-start the system power supply prior to energy harvesting operation.Semiconductor Research Corporation. Interconnect Focus CenterSemiconductor Research Corporation. C2S2 Focus CenterNational Institutes of Health (U.S.) (Grant K08 DC010419)National Institutes of Health (U.S.) (Grant T32 DC00038)Bertarelli Foundatio

Design and Test of a Gate Driver with Variable Drive and Self-Test Capability Implemented in a Silicon Carbide CMOS Process

Discrete silicon carbide (SiC) power devices have long demonstrated abilities that outpace those of standard silicon (Si) parts. The improved physical characteristics allow for faster switching, lower on-resistance, and temperature performance. The capabilities unleashed by these devices allow for higher efficiency switch-mode converters as well as the advance of power electronics into new high-temperature regimes previously unimaginable with silicon devices. While SiC power devices have reached a relative level of maturity, recent work has pushed the temperature boundaries of control electronics further with silicon carbide integrated circuits. The primary requirement to ensure rapid switching of power MOSFETs was a gate drive buffer capable of taking a control signal and driving the MOSFET gate with high current required. In this work, the first integrated SiC CMOS gate driver was developed in a 1.2 μm SiC CMOS process to drive a SiC power MOSFET. The driver was designed for close integration inside a power module and exposure to high temperatures. The drive strength of the gate driver was controllable to allow for managing power MOSFET switching speed and potential drain voltage overshoot. Output transistor layouts were optimized using custom Python software in conjunction with existing design tool resources. A wafer-level test system was developed to identify yield issues in the gate driver output transistors. This method allowed for qualitative and quantitative evaluation of transistor leakage while the system was under probe. Wafer-level testing and results are presented. The gate driver was tested under high temperature operation up to 530 degrees celsius. An integrated module was built and tested to illustrate the capability of the gate driver to control a power MOSFET under load. The adjustable drive strength feature was successfully demonstrated

Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic

The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this work we present a number of new CMOS logic families, Charge Recovery Logic (CRL) as well as the much improved Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically. Operating quasistatically, these logic families have an energy dissipation that drops linearly with operating frequency, i.e., their power consumption drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The circuit techniques in these new families rely on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its logical inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. We demonstrate the low energy operation of SCRL by presenting the results from the testing of the first fully quasistatic 8 x 8 multiplier chip (SCRL-1) employing SCRL circuit techniques