The scope of this research work is to develop digital standard cell and I/O cell libraries operable at 5V power supply and operable up to 125�C using Peregrine 0.5um 3.3 V process. Device geometries are selected based on Ion/Ioff ratios at 125�C. The cell schematic, layout and abstracted views are generated for both the libraries The Standard cell and I/O libraries are characterized for timing and power and the characterization data is realized in various formats compatible with logic synthesis and place and route tools. The pads have been tested for robustness to ESD. A tutorial on abstraction of standard cells and IO cells is prepared using the Cadence Abstract Generator.School of Electrical & Computer Engineerin
