Neurofuzzy controller based full vehicle nonlinear active suspension systems

To design a robust controller for active suspension systems is very important for guaranteeing the riding comfort for passengers and road handling quality for a vehicle. In this thesis, the mathematical model of full vehicle nonlinear active suspension systems with hydraulic actuators is derived to take into account all the motions of the vehicle and the nonlinearity behaviours of the active suspension system and hydraulic actuators. Four robust control types are designed and the comparisons among the robustness of those controllers against different disturbance types are investigated to select the best controller among them. The MATLAB SIMULINK toolboxes are used to simulate the proposed controllers with the controlled model and to display the responses of the controlled model under different types of disturbance. The results show that the neurofuzzy controller is more effective and robust than the other controller types. The implementation of the neurofuzzy controller using FPGA boards has been investigated in this work. The Xilinx ISE program is employed to synthesis the VHDL codes that describe the operation of the neurofuzzy controller and to generate the configuration file used to program the FPGA. The ModelSim program is used to simulate the operation of the VHDL codes and to obtain the expected output data of the FPGA boards. To confirm that FPGA the board used as the neurofuzzy controller system operated as expected, a MATLAB script file is used to compare the set of data obtained from the ModelSim program and the set of data obtained from the MATLAB SIMULINK model. The results show that the FPGA board is effective to be used as a neurofuzzy controller for full vehicle nonlinear active suspension systems. The active suspension system has a great performance for vibration isolation. However the main drawback of the active suspension is that it is high energy consumptive. Therefore, to use this suspension system in the proposed model, this drawback should be solved. Electromagnetic actuators are used to convert the vibration energy that arises from the rough road to useful electrical energy to reduce the energy consumption by the active suspension systems. The results show that the electromagnetic devices act as a power generator, i.e. the vibration energy excited by the rough road surface has been converted to a useful electrical energy supply for the actuators. Furthermore, when the nonlinear damper models are replaced by the electromagnetic actuators, riding comfort and the road handling quality are improved. As a result, two targets have been achieved by using hydraulic actuators with electromagnetic suspension systems: increasing fuel economy and improving the vehicle performance

Partially reconfigurable SDR solution on FPGA

Abstract. Software-defined radios (SDR) have become more common in order to answer the increasing complexity of wireless communication standards. The flexibility offered by SDR technology in return makes it possible to create and implement even more complex standards so there exists a mutual evolution cycle. One of the technological opportunities pursued on SDR is changing the waveforms on the fly. The standards challenge the SDR development. Computing throughput needs to be high enough, the end product has to be energy efficient, and all of this must be accomplished as cheaply as possible. SDRs have a wide range of implementation opportunities from complete software designs to more hardware oriented with higher level software control. The extreme ends of these approaches suffer from energy dissipation and design cost issues, respectively. The compromises include application specific architectures and reconfigurable hardware. Solutions vary from software to hardware between cases and depending on the needs. This thesis concentrates on investigating partial reconfigurability on a field-programmable gate array (FPGA) in an SDR application. Based on the results, partial reconfigurability is an attractive mean to bolster SDR functionalities. Although the energy efficiency of the employed FPGA solution is inferior to using an application-specific integrated circuit (ASIC), the flexibility and cost of design set them apart. This study focuses on partial reconfiguration on Xilinx FPGA devices but it may show benefits for other devices that can utilize partial reconfiguration on their designs.Osittain uudelleenohjelmoitava ohjelmistoradio FPGA-piirillä. Tiivistelmä. Ohjelmistoradiot ovat yleistyneet entistä kehittyneempien langattomien kommunikointimenetelmien myötä ja tarpeesta vastata näiden vaatimuksiin. Samalla ohjelmistoradioiden joustavuus mahdollistaa uusien ja kompleksisempien standardien kehittämisen. Tätä voi pitää molemminpuolisena kehityssyklinä. Aaltomuotojen nopea vaihtaminen lennosta ohjelmistoradion ollessa käytössä on yksi kehityksen alla oleva teknologia. Kommunikointistandardit haastavat ohjelmistoradioiden kehityksen erilaisilla vaatimuksillaan. Esimerkiksi laskentatehon tulee olla korkea, lopputuotteen energiatehokas ja tämän tulee tapahtua mahdollisimman edullisesti. Ohjelmistoradioiden toteutukset vaihtelevat aina vahvoista ohjelmistopohjaisista arkkitehtuureista enemmän laitteistoon tukeutuviin versioihin. Ääripäissä tässä spektrissä ohjelmistoihin perustuvat toteutukset eivät ole riittävän energiatehokkaita ja laitteistoratkaisujen hinnat nousevat helposti korkealle. Keskitien ratkaisuja ovat sovelluskohtaiset arkkitehtuurit ja uudelleen ohjelmoitavat laitteistot. Implementaatiot vaihtelevat ohjelmisto-laitteisto skaalalla riippuen tarpeesta ja tilanteesta. Tämä opinnäytetyö keskittyy tutkimaan osittaista uudelleenohjelmoimista FPGA-piireillä ohjelmistoradion yhteydessä. Tulosten perusteella osittainen uudelleen ohjelmointi on houkutteleva tapa tehostaa ohjelmistoradioita. Vaikka FPGA-piirien energiatehokkuus ei ole yhtä hyvä kuin ASIC-toteutusten, niiden joustavuus ja suunnittelukustannukset ovat paremmat. Vaikka tämä työ keskittyy osittaiseen uudelleenohjelmointiin Xilinxin FPGA-piireillä, voi siitä olla hyötyä muissa tutkimuksissa ja laitteissa

The CMS Drift Tube Trigger Track Finder

Muons are among the decay products of many new particles that may be discovered at the CERN Large Hadron Collider. At the first trigger level the identification of muons and the determination of their transverse momenta and location is performed by the Drift Tube Trigger Track Finder in the central region of the Compact Muon Solenoid experiment, using track segments detected in the Drift Tube muon chambers. Track finding is performed both in pseudorapidity and azimuth. Track candidates are ranked and sorted, and the best four are delivered to the subsequent high level trigger stage. The concept, design, control and simulation software as well as the expected performance of the system are described. Prototyping, production and tests are also summarized

eVentos 2 - Autonomous sailboat control

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de ComputadoresSailboat navigation started as a way to explore the world. Even though performance is significantly lower than that of a motorboat, in terms of resources, these vessels still are the best low-cost solutions. On the past, navigation depended greatly on estimates or on the stars. Nowadays it depends on precise data provided by a variety of electronic devices, independent from the user’s location. Autonomous sailboats are vessels that use only the wind for propulsion and have the capacity to control its sails and rudders without human intervention. These particularities give them almost unlimited autonomy and a very valuable ability to fulfill long term missions on the sea, such as collecting oceanographic data, search and rescue or surveillance. This dissertation presents a fuzzy logic controller for autonomous sailboats based on a proposed set of sensors, namely a GPS receiver, a weather meter and an electronic compass. Following a basic navigation approach, the proposed set of sensorswas studied in order to obtain an effective group of variables for the controller’s fuzzy sets, and rules for its rule base. In the end, four fuzzy logic controllers were designed, one for the sail(to maximize speed) and three for the rudder (in order to comply with all navigation situations). The result is a sailboat control system capable of operation in a low cost platform such as an Arduino prototyping board. Simulated results obtained from a data set of approximately 100 tests to each controller back up the theory presented for the controller’s operation, since physical experimentation was not possible

マルチレベル並列化とアプリケーション指向データレイアウトを用いるハードウェアアクセラレータの設計と実装

学位の種別: 課程博士審査委員会委員 : （主査）東京大学教授 稲葉 雅幸, 東京大学教授 須田 礼仁, 東京大学教授 五十嵐 健夫, 東京大学教授 山西 健司, 東京大学准教授 稲葉 真理, 東京大学講師 中山 英樹University of Tokyo(東京大学

Data acquisition for Germanium-detector arrays

Die Wandlung von analogen zu digitalen Signalen und die anschließende online/offline Verarbeitung ist die technologische Voraussetzung zahlreicher Experimente. Für diese Aufgaben werden häufig sogenannte Analog-Digital-Wandler (ADC) und FPGAs („field-programmable gate array“) eingesetzt. Die vorliegende Arbeit beschreibt die Evaluierung der FPGA und ADC Komponenten für die geplante FlashCAM 2.0 DAQ (FC2.0 DAQ). Die Entwicklung der ersten FlashCAM (1.0) DAQ (FC1.0 DAQ) wurde unter Federführung des Max-Planck-Instituts für Kernphysik im Jahre 2012 begonnen und war ursprünglich eine exklusive Entwicklung für das Cherenkov Telescope Array (CTA) Experiment. In der Zwischenzeit wird FlashCAM in zahlreichen Experimenten (HESS, HAWK, LEGEND-200, etc.) eingesetzt, die sowohl Photomultiplier (PMTs) als auch High Purity Germanium (HPGe) Detektoren umfassen. Beide Detektorentypen unterscheiden sich massiv in ihren Anforderungen und können auch von der neuen DAQ abgedeckt werden. Das Themengebiert der Arbeit umfasst den gesamten funktionellen Umfang einer modernen DAQ. Moderne DAQ Systeme benötigen eine möglichst hohe Read Out Performance zwischen dem DAQ Board und dem es kontrollierenden Server. Die Umsetzung eines leistungsfähigen Firmware Designs und das Design einer hierauf angepassten Hardware/Softwareschnittstelle wird am Beispiel der Zynq Familie vorgestellt. Die Zynq-Familie von Xilinx ist von besonderem Interesse, da der Hardwarehersteller Trenz Elektronik ein flexibles, einfach aufsteckbares Modulkonzept mit verschiedenen SoCs der Zynq-Serie anbietet. Neben der Read Out Performance einer DAQ ist ihre Auflösungsgrenze von entscheidender Bedeutung für das Gelingen des finalen Experiments. Die verwendete FADC Karte muss sich daher durch exzellente SNR und Linearitätseigenschaften auszeichnen. Die Evaluierung solcher FADC Karten setzt ein Testsetup voraus, dass in Signalreinheit und Stabilität die hohen Anforderungen der devices under test übertreffen muss. Praktisch sind diese Bedingungen nur unter hohem (Kosten) Aufwand erreichbar. Im Rahmen der Arbeit wurden daher auch alternative Testkonzepte entwickelt, die mit akzeptablen Abstrichen in der Genauigkeit eine Messung im experimentellen Umfeld ermöglichen können. Da sich die Themengebiete in ihrem Inhalt deutlich unterscheiden, wurde die vorliegende Arbeit in zwei Themenkomplexe aufgeteilt. Der erste Teil der Arbeit beschäftigt sich mit dem Einsatz der Zynq Familie in der geplanten „FlashCAM“ Nachfolger DAQ. Der zweite Teil widmet sich der ADC Nichtlinearitätsbestimmung. Die wichtigsten Ergebnisse der Arbeit lassen sich folgt zusammenfassen: ▪ Die „High Performance“ (HP) Schnittstellen der Zynq-UltraScale+ haben eine aussetzerfreie Bandbreite von 2.4 GB/s in den externen Arbeitsspeicher der Trenz Module. Wird noch zusätzlich die standardmäßig vorhandene 1 Gb PS-Ethernet Verbindung betrieben, verbleibt der CPU noch eine Bandbreite von mindestens 0.5 GB/s in den Arbeitsspeicher. Im Fall der Zynq-7000 Serie ist eine effiziente Implementierung der HP Schnittstellen schwierig, da die CPU nur vergleichsweise niedrige Arbeitsspeicherzugriffsraten erreicht. Die HP Schnittstellen sind eine wichtige Designalternative da ein durchgehender Datentransfer in den externen Arbeitsspeicher ein Design ermöglichen würde dass weniger stark durch den verfügbaren FPGA internen Speicher begrenzt ist. Dies wäre besonders für Anwendungen in der HPGe-Spektroskopie wünschenswert, da der praktische Nutzen des verwendeten Designs stark von der zur Verfügung stehende Puffergröße abhängt. ▪ Die “Accelerator Coherency” Schnittstelle (ACP) ermöglicht ein direkter Datentransfer aus der FPGA in den Cache der Zynq-CPU. Die entworfene ACP-CMA hat eine Bandweite von bis zu 2.4 GB/s und bietet für Cache-CPU Zugriffe noch ausreichend Reserve. Dass die Zynq-CPU die Cachedaten ohne ein Abwürgen der ACP-CMA verarbeiten kann, ist entscheidend. Wäre dies nicht der Fall könnte die CPU im Parallelbetrieb von Ethernet und ACP-CMA nicht die notwendigen Vorarbeiten zur Ethernet-Übertragung („Event Building“) bewältigen. In der Evaluierung wurde eine maximale Event Building Bandbreite von 0.7 GB/s festgestellt. Wahrscheinlich ist die reale maximale Bandbreite deutlich höher anzusiedeln. Einschränkend muss betont werden, dass in praktischen Applikationen zusätzliche Einschränkungen in Kraft treten, die de-facto einen kontinuierlichen Betrieb der ACP-CMA unmöglich machen. Diese Einschränkungen – die nicht prinzipieller Natur sind - wurden in der durchgeführten Ermittlung nicht berücksichtigt. Da weiterhin alle Zynq-FPGAs über einen Cache verfügen, ist die ACP-CMA eine Designlösung, die auf allen verfügbaren Zynq-FPGAs sinnvoll implementiert werden kann. Dies unterscheidet sie von der entwickelten HP-DMA, die häufig nur für Implementierungen in einer Zynq-UltraScale FPGA interessant ist. ▪ Der neuentwickelte FC2.0 Prototype wurde bereits in experimentellen Setups eingesetzt. Als Anwendungsbeispiel dient die Messung und Analyse eines γ-ray Spektrums eines HPGe-Detektors. ▪ Der Erfolg einer ADC Nichtlinearitätsbestimmungen ist stark von der Signalreinheit des verwendeten Eingangssignal abhängig. In Simulationen konnte gezeigt werden, dass die neu entwickelten Verfahren nur relativ schwach durch Pulsernichtlinearitäten verfälscht werden. Einen praktischen Vergleich zwischen den neuen und einer klassischen Methode konnte keinen signifikanten Unterschied feststellen. Die untersuchten Methoden können daher für eine zukünftige Implementation in FC2.0 empfohlen werden

A novel parallel algorithm for surface editing and its FPGA implementation

A thesis submitted to the University of Bedfordshire in partial fulfilment of the requirements for the degree of Doctor of PhilosophySurface modelling and editing is one of important subjects in computer graphics. Decades of research in computer graphics has been carried out on both low-level, hardware-related algorithms and high-level, abstract software. Success of computer graphics has been seen in many application areas, such as multimedia, visualisation, virtual reality and the Internet. However, the hardware realisation of OpenGL architecture based on FPGA (field programmable gate array) is beyond the scope of most of computer graphics researches. It is an uncultivated research area where the OpenGL pipeline, from hardware through the whole embedded system (ES) up to applications, is implemented in an FPGA chip. This research proposes a hybrid approach to investigating both software and hardware methods. It aims at bridging the gap between methods of software and hardware, and enhancing the overall performance for computer graphics. It consists of four parts, the construction of an FPGA-based ES, Mesa-OpenGL implementation for FPGA-based ESs, parallel processing, and a novel algorithm for surface modelling and editing. The FPGA-based ES is built up. In addition to the Nios II soft processor and DDR SDRAM memory, it consists of the LCD display device, frame buffers, video pipeline, and algorithm-specified module to support the graphics processing. Since there is no implementation of OpenGL ES available for FPGA-based ESs, a specific OpenGL implementation based on Mesa is carried out. Because of the limited FPGA resources, the implementation adopts the fixed-point arithmetic, which can offer faster computing and lower storage than the floating point arithmetic, and the accuracy satisfying the needs of 3D rendering. Moreover, the implementation includes Bézier-spline curve and surface algorithms to support surface modelling and editing. The pipelined parallelism and co-processors are used to accelerate graphics processing in this research. These two parallelism methods extend the traditional computation parallelism in fine-grained parallel tasks in the FPGA-base ESs. The novel algorithm for surface modelling and editing, called Progressive and Mixing Algorithm (PAMA), is proposed and implemented on FPGA-based ES’s. Compared with two main surface editing methods, subdivision and deformation, the PAMA can eliminate the large storage requirement and computing cost of intermediated processes. With four independent shape parameters, the PAMA can be used to model and edit freely the shape of an open or closed surface that keeps globally the zero-order geometric continuity. The PAMA can be applied independently not only FPGA-based ESs but also other platforms. With the parallel processing, small size, and low costs of computing, storage and power, the FPGA-based ES provides an effective hybrid solution to surface modelling and editing

Dynamically reconfigurable bio-inspired hardware

During the last several years, reconfigurable computing devices have experienced an impressive development in their resource availability, speed, and configurability. Currently, commercial FPGAs offer the possibility of self-reconfiguring by partially modifying their configuration bitstream, providing high architectural flexibility, while guaranteeing high performance. These configurability features have received special interest from computer architects: one can find several reconfigurable coprocessor architectures for cryptographic algorithms, image processing, automotive applications, and different general purpose functions. On the other hand we have bio-inspired hardware, a large research field taking inspiration from living beings in order to design hardware systems, which includes diverse topics: evolvable hardware, neural hardware, cellular automata, and fuzzy hardware, among others. Living beings are well known for their high adaptability to environmental changes, featuring very flexible adaptations at several levels. Bio-inspired hardware systems require such flexibility to be provided by the hardware platform on which the system is implemented. In general, bio-inspired hardware has been implemented on both custom and commercial hardware platforms. These custom platforms are specifically designed for supporting bio-inspired hardware systems, typically featuring special cellular architectures and enhanced reconfigurability capabilities; an example is their partial and dynamic reconfigurability. These aspects are very well appreciated for providing the performance and the high architectural flexibility required by bio-inspired systems. However, the availability and the very high costs of such custom devices make them only accessible to a very few research groups. Even though some commercial FPGAs provide enhanced reconfigurability features such as partial and dynamic reconfiguration, their utilization is still in its early stages and they are not well supported by FPGA vendors, thus making their use difficult to include in existing bio-inspired systems. In this thesis, I present a set of architectures, techniques, and methodologies for benefiting from the configurability advantages of current commercial FPGAs in the design of bio-inspired hardware systems. Among the presented architectures there are neural networks, spiking neuron models, fuzzy systems, cellular automata and random boolean networks. For these architectures, I propose several adaptation techniques for parametric and topological adaptation, such as hebbian learning, evolutionary and co-evolutionary algorithms, and particle swarm optimization. Finally, as case study I consider the implementation of bio-inspired hardware systems in two platforms: YaMoR (Yet another Modular Robot) and ROPES (Reconfigurable Object for Pervasive Systems); the development of both platforms having been co-supervised in the framework of this thesis