On the robustness of ultra-high voltage 4H-SiC IGBTs with an optimized retrograde p-well

The robustness of ultra-high voltage (>10kV) SiC IGBTs comprising of an optimized retrograde p-well is investigated. Under extensive TCAD simulations, we show that in addition to offering a robust control on threshold voltage and eliminating punch-through, the retrograde is highly effective in terms of reducing the stress on the gate oxide of ultra-high voltage SiC IGBTs. We show that a 10 kV SiC IGBT comprising of the retrograde p-well exhibits a much-reduced peak electric field in the gate oxide when compared with the counterpart comprising of a conventional p-well. Using an optimized retrograde p-well with depth as shallow as 1 μm, the peak electric field in the gate oxide of a 10kV rated SiC IGBT can be reduced to below 2 MV.cm -1 , a prerequisite to achieve a high-degree of reliability in high-voltage power devices. We therefore propose that the retrograde p-well is highly promising for the development of>10kV SiC IGBTs

OXIDATION OF SILICON - THE VLSI GATE DIELECTRIC

Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale.The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that P-b concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen.Finally, the roles of contamination, particles, metals, hydrocarbons etc are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above

Cause and Effect of Threshold-Voltage Instability on the Reliability of Silicon-Carbide MOSFETs

A significant instability of the threshold voltage (VT) in silicon carbide (SiC) MOSFETs in response to gate-bias and ON-state current stressing was discovered and examined as a function of bias, temperature, and time. It was determined that the likely mechanism causing this effect is the charging and discharging of gate-oxide traps, located close to the interface of the SiC conducting channel, via a direct tunneling mechanism. High-temperature reverse-bias induced leakage current in the OFF-state was identified as a potential failure mode. A simultaneous two-way tunneling model was developed, based on an existing one-way tunneling model, to simulate the time-dependent and field-dependent charging and discharging of the near-interfacial oxide traps in response to an applied gate-bias stress. The simulations successfully matched experimental results, both with respect to measurement time and to bias-stress time as a function of gate bias. Experimental results were presented, showing that the VT instability increases with both increasing gate-bias-stress time and bias-stress magnitude. The measurement conditions, including gate-ramp speed and direction, were shown to have a significant influence on the measured result, with a 20-μs measurement revealing instabilities three times greater than those at standard 1-s measurement speeds, whereas 1-ks measurements showed shifts only half as large. High-temperature bias stressing was found to cause even more significant increases in the VT instability. ON-state current stressing was found to also increase the VT instability, due to self-heating effects. VT shifts as large as 2 V were reported, with the number of calculated oxide traps switching charge state varying between 1×1011 and 8×1011 cm–2, depending on processing, stress, and measurement conditions. The standard post-oxidation NO anneal was shown to reduce the number of active oxide traps by about 70 percent. The dominant oxide trap was identified as an E-prime-center type defect—a weak Si-Si bond due to an oxygen vacancy which has been broken during processing or subsequent device stressing. The large increase in bias-stress induced VT instability at temperatures above 100 °C was explained by an increase in the number of active E-prime-center type defects. Existing reliability qualification standards based on silicon device technology are inadequate for SiC MOSFETs and need to be revised, with particular attention paid to the measurement conditions

Device physics and failure mechanisms of deep submicron gate GaN HEMTs for microwave and millimeter-wave applications

openThis thesis presents the findings of a comprehensive characterization study on GaN-based, gate-scaled HEMTs (with Lg < 0.15 µm) for RF applications. The investigation considers performance, stability, and reliability aspects. Specifically, static and dynamic measurements were conducted for the devices under test to assess the influence of short-channel effects and deep-level traps on their characteristics. This involved double-pulse measurements both in OFF and semi-ON state stress and transient measurements. The observed results are compared with those reported in the literature to determine the nature and location of traps responsible for performance variations. In the end stress test were performed to investigate the reliability of the devices. This research contributes to a deeper understanding of the underlying mechanisms and provides valuable insights for the optimization of future GaN-based device designs.This thesis presents the findings of a comprehensive characterization study on GaN-based, gate-scaled HEMTs (with Lg < 0.15 µm) for RF applications. The investigation considers performance, stability, and reliability aspects. Specifically, static and dynamic measurements were conducted for the devices under test to assess the influence of short-channel effects and deep-level traps on their characteristics. This involved double-pulse measurements both in OFF and semi-ON state stress and transient measurements. The observed results are compared with those reported in the literature to determine the nature and location of traps responsible for performance variations. In the end stress test were performed to investigate the reliability of the devices. This research contributes to a deeper understanding of the underlying mechanisms and provides valuable insights for the optimization of future GaN-based device designs

Novel Developments and Challenges for the SiC Power Devices

Silicon Carbide (SiC) is believed to be a revolutionary semiconductor material for power devices of the future; many SiC power devices have emerged as superior alternative power switch technology, especially in harsh environments with high temperature or high electric field. In this chapter, the challenges and recent developments of SiC power devices are discussed. The first part is focused on SiC power diodes including SiC Schottky barrier diode (SBD), SiC PiN diodes (PiN,) SiC junction/Schottky diodes (JBS), then SiC UMOSFETs, DMOSFETs and several MESFETs are introduced, and the third part is about SiC bipolar devices such as BJT and IGBT. Finally, the challenges during the development of SiC power devices, especially about its material growth and packaging are discussed