The Efficacy of Programming Energy Controlled Switching in Resistive Random Access Memory (RRAM)

Current state-of-the-art memory technologies such as FLASH, Static Random Access Memory (SRAM) and Dynamic RAM (DRAM) are based on charge storage. The semiconductor industry has relied on cell miniaturization to increase the performance and density of memory technology, while simultaneously decreasing the cost per bit. However, this approach is not sustainable because the charge-storage mechanism is reaching a fundamental scaling limit. Although stack engineering and 3D integration solutions can delay this limit, alternate strategies based on non-charge storage mechanisms for memory have been introduced and are being actively pursued. Resistive Random Access Memory (RRAM) has emerged as one of the leading candidates for future high density non-volatile memory. The superior scalability of RRAMs is based on the highly localized active switching region and filamentary conductive path. Coupled with its simple structure and compatibility with complementary metal oxide semiconductor (CMOS) processes; RRAM cells have demonstrated switching performance comparable to volatile memory technologies such as DRAMs and SRAMs. However, there are two serious barriers to RRAM commercialization. The first is the variability of the resistance state which is associated with the inherent randomness of the resistive switching mechanism. The second is the filamentary nature of the conductive path which makes it susceptible to noise. In this experimental thesis, a novel program-verify (P-V) technique was developed with the objective to specifically address the programming errors and to provide solutions to the most challenging issues associated with these intrinsic failures in current RRAM technology. The technique, called Compliance-free Ultra-short Smart Pulse Programming (CUSPP), utilizes sub-nanosecond pulses in a compliance-free setup to minimize the programming energy delivered per pulse. In order to demonstrate CUSPP, a custom-built picosecond pulse generator and feedback control circuit was designed. We achieved high (108 cycles) endurance with state verification for each cycle and established high-speed performance, such as 100 ps write/erase speed and 500 kHz cycling rate of HfO2-based RRAM cells. We also investigate switching failure and the short-term instability of the RRAM using CUSPP

Resistive switching in ALD metal-oxides with engineered interfaces

L'abstract è presente nell'allegato / the abstract is in the attachmen

OXIDE-BASED MEMRISTIVE DEVICES BY BLOCK COPOLYMER SELF-ASSEMBLY

Oxide-based memristive systems represent today an emerging class of devices with a significant potential in memory, logic, and neuromorphic circuit applications. These devices have a simple capacitor structure and promise superior scalability together with favorable memory performances. This thesis presents a study of resistive switching phenomena in HfOx-based nanoscale memristive devices, with focus on material properties and development of bottom-up approaches for the fabrication of structures with dimension down to the nanoscale. One of the main issues for practical applications regarding device variability is first assessed by doping hafnium oxide films with different concentrations of aluminum atoms. Testing devices are analyzed by physico-chemical and electrical techniques in order to define the effect of oxide doping on the device properties. In the following part of the thesis, the scalability limit is explored in very high density arrays of nanodevices produced exploiting a lithographic approach based on the bottom-up self-assembly of block copolymer templates. This technique allows a tight control over the size and density of the defined features, and the possibilities offered by block copolymer patterning are here discussed. Electrical measurements of the nanodevices are performed through conductive atomic force microscopy. The device variability is examined and related to the inherent oxide non-homogeneity at the nanoscale, while a non-volatile switching of the resistance of the nanodevices is demonstrated. Further, this analysis draws the attention to a crosstalk phenomenon occurring at the nanoscale in a continuous thin film geometry. This result suggests to select different system configurations. A promising technique based on selective reactions with one copolymer block is finally discussed which allows the direct production of oxide patterns from block copolymer templates avoiding a pattern transfer process. In conclusion, the results reported in this thesis highlight the high scalability potential of oxide-based memristive devices, providing a missing piece of information for the understanding and practical development of very high density arrays

Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

This thesis focuses mainly on the co-integration of vertical nanowiren-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), whereMOVPE grown vertical InAs-GaSb heterostructure nanowires areused for realizing monolithically integrated and co-processed all-III-V CMOS.Utilizing a bottom-up approach based on MOVPE grown nanowires enablesdesign flexibilities, such as in-situ doping and heterostructure formation,which serves to reduce the amount of mask steps during fabrication. By refiningthe fabrication techniques, using a self-aligned gate-last process, scaled10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabledby greatly improved p-type MOSFET performance reaching a maximumtransconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipationfor CMOS circuits requires good threshold voltage VT matching of the n- andp-type device, which is also demonstrated for basic inverter circuits. Thevarious effects contributing to VT-shifts are also studied in detail focusing onthe InAs channel devices (with highest transconductance of 2.6 mA/μm), byusing Electron Holography and a novel gate position variation method (PaperV).The advancements in all-III-V CMOS integration spawned individual studiesinto the strengths of the n- and p-type III-V devices, respectively. Traditionallymaterials such as InAs and InGaAs provide excellent electrontransport properties, therefore they are frequently used in devices for highfrequency RF applications. In contrast, the III-V p-type alternatives have beenlacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFETchannel, was designed and enabled by new manufacturing techniques, whichallowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs(Paper III). The new fabrication method allowed for integration of deviceswith symmetrical contacts as compared to previous work which relied on atunnel-contact at the source-side. By modelling based on measured data fieldeffecthole mobility of 70 cm2/Vs was calculated, well in line with previouslyreported studies on GaSb nanowires. The oxidation properties of the GaSbgate-stack was further characterized by XPS, where high intensities of xraysare achieved using a synchrotron source allowed for characterization ofnanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPSmeasurements, enabled a study of the time-dependence during full removalof GaSb native oxides.The last focus of the thesis was building on the existing strengths of verticalheterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,these devices demonstrate high-current densities (gm >3 mS/μm) and excellentmodulation properties (off-state current down to 1 nA/μm). However,minimizing the parasitic capacitances, due to various overlaps originatingfrom a low access-resistance design, has proven difficult. Therefore, newmethods for spacers in both the vertical and planar directions was developedand studied in detail. The new fabrication methods including sidewall spacersachieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which isthe established limit by optimized high-speed devices. The vertical spacertechnology, using SiO2 on the nanowire sidewalls, is further improved inthis thesis which enables new co-integration schemes for memory arrays.Namely, the refined sidewall spacer method is used to realize selective recessetching of the channel and reduced capacitance for large array memoryselector devices (InAs channel) vertically integrated with Resistive RandomAccess Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-memristor (1T1R) demonstrator cell shows excellent endurance and retentionfor the RRAM by maintaining constant ratio of the high and low resistive state(HRS/LRS) after 106 switching cycles

Defect Induced Aging and Breakdown in High-k Dielectrics

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

Defect Engineering in HfO2/TiN-based Resistive Random Access Memory (RRAM) Devices by Reactive Molecular Beam Epitaxy

Recently, there has been huge interest in emerging memory technologies, spurred by the ever increasing demand for storage capacities in various applications like Internet of Things (IoT), Big Data, etc. CMOS based flash memory, the current mainstay of the memory technology, has been able to increase its density by scaling down to a 16 nm node and further implementation of 3D architectures. However, flash memory is expected to soon run into disadvantage due to challenges in further scaling. Therefore, extensive efforts are being made towards developing new devices for the next generation of non-volatile memories with the combined advantages of flash memory like non-volatility, high density, low cost and low power consumption as well as high speed performance of DRAM. Among the many competitors, resistive random access memories (RRAM) based on resistive switching in oxides are promising due to its simple metal-insulator-metal (MIM) structure, fast switching speeds (<10 ns), excellent scalability (<10 nm) and potential for multi-level switching. RRAM devices based on the popular dielectric-metal gate combination of hafnium oxide (HfO2) and titanium nitride (TiN), which is the subject of research in this work, are particularly interesting due to its compatibility with existing CMOS technology in addition to the aforementioned advantages. Though prototype RRAM chips have already been demonstrated, key problems for commercial realization of RRAM include large variability and insufficient understanding of the complex switching physics. Resistive switching mechanism in oxides is generally understood to be mediated via the transport of oxygen ions leading to the formation of a conductive filament composed of oxygen vacancy defects. Appropriate defect engineering approaches offer potential towards tailoring the switching behavior as well as improving the performance and yield of HfO2-RRAM. In this thesis, the impact of pre-induced defects on the resistive switching behavior of HfO2-RRAM is investigated in detail and our results are presented. Defect engineered oxide thin films were deposited using reactive molecular beam epitaxy (RMBE) to fabricate metal oxide/TiN based devices. RMBE technique offers the unique possibility to precisely and reproducibly control the oxygen stoichiometry of the thin films in a wide range. Using RMBE, defects were introduced in polycrystalline HfOx thin films intrinsically by oxygen stoichiometry engineering and extrinsically via impurity doping (trivalent lanthanum and pentavalent tantalum). Both the studies were performed at at CMOS compatible deposition temperatures (< 450 °C) with an eye on practical applications. Prior to tantalum doping in HfO2, oxygen stoichiometry engineering studies were also performed in amorphous tantalum oxide (TaOx) thin films to identify the oxidation conditions of tantalum metal. The density of oxygen stoichiometry engineered thin films of HfOx and TaOx could be tuned in a wide range from that of the bulk oxide density to close to metallic density. High degree of oxygen deficiency in oxides led to the formation of defect states near the Fermi level as well as multiple oxidation states of the metal, as observed by X-ray photoelectron spectroscopy (XPS). The pure stoichiometric hafnium oxide films crystallize as expected in a stable monoclinic structure (m-HfO2) whereas, oxygen deficient HfOx thin films were found to crystallize in vacancy stabilized tetragonal like structure (t-HfO2-x). Impurity doping also led to the stabilization of higher symmetry tetragonal (t-Ta:HfOx) or cubic structures (c-La:HfOx) depending on the ionic radii of the dopant. The growth of TiN thin films was also investigated using RMBE. The devices used for electrical studies in this work mostly involved deposition of oxides by RMBE on polycrystalline TiN/Si electrodes after ex-situ transfer for further deposition. Therefore, RMBE grown TiN thin film electrodes with similar or better quality would allow in-situ uninterrupted deposition of subsequent oxide layers in future to form cleaner interfaces. Optimized conditions for growth of epitaxial TiN films on the commercially relevant (001) oriented silicon and c-cut sapphire substrates were established, with focus on achieving smooth surfaces and low resistivity. High quality epitaxial TiN(111)||Al2O3(0001) and TiN(001)||Si(001) films with a low resistivity (20-200 uOhm.cm) were achieved, in spite of the large lattice mismatch. Very low surface roughness, characterized by a streaky reflection high energy electron diffraction (RHEED) pattern during TiN film growth was additionally obtained, by tuning the Ti/N flux ratios. Oxygen engineered HfOx/TiN devices were further electrically characterized to obtain I-V characteristics during quasi-static DC switching. Usually, an initial electroforming step (high voltages) is required to obtain further reproducible switching operation (at lower voltages). High device to device variability in RRAM is typically associated with the stochastic nature of electroforming process which increases at higher forming voltages. Using highly oxygen deficient HfOx and TaOx films, the forming voltages were found to be reduced to levels close to operating voltages, paving the way for forming-free devices. However, the use of high defect concentration adds to increasing the complexity of the switching mechanism. This is reflected in the rather complex and dissimilar switching behaviors observed in the myriad of similar RRAM devices reported in the rapidly growing literature. Using model Pt/HfOx/TiN-based device stacks; it is shown that a well-controlled oxygen stoichiometry governs the filament formation and the (partial) occurrence of multiple resistive switching modes (bipolar, unipolar, threshold, complementary). These findings fuel a better fundamental understanding of the underlying phenomena for future theoretical considerations. The oxygen vacancy concentration is found to be the key factor in manipulating the balance between electric field and Joule heating during formation, rupture (reset), and reformation (set) of the conductive filaments in the dielectric. While a bipolar switching occurs in all the devices irrespective of defect concentration, switching modes like unipolar and threshold switching is favored only at higher oxygen stoichiometry. This suggests the suppression of thermal effects via higher heat dissipation and lowered concentration gradient of oxygen vacancies in oxygen deficient devices. A qualitative switching model based on the drift, diffusion and thermophoresis of oxygen ions is suggested to account for the partial occurrence of various switching modes depending on the oxygen stoichiometry. Further, the evolution or drift of high resistance states during endurance test of the common bipolar operation is compared for HfO2 and HfO1.5 based devices and interpreted using the quantum point contact (QPC) model. Similar observations regarding switching modes were also obtained in oxygen engineered Pt/TaOx/TiN devices, therefore allowing the findings to be generalized to other filamentary resistive switching oxides and contributing towards developing a unified switching model. Besides finding application as non-volatile memory, RRAM devices are also promising for hardware implementation of neuromorphic computing. This is motivated by the possibility of multi-level switching or gradual (analog) modulation of resistance in an RRAM device which can emulate biological synapses. Defect engineering approaches have thus been investigated in Pt/hafnium oxide/TiN devices for tuning the DC I-V switching dynamics to achieve multi-level or gradual switching electronic synapses. Higher contribution of thermal effects in pure stoichiometric HfO2 typically results in a single sharp set process and abrupt sharp current jumps during the reset process during a conventional bipolar operation. By using ~18% La-doped HfOx based device, a completely gradual reset behavior with a higher ON/OFF ratio could be achieved during the bipolar reset operation. This is likely related to filament stabilization around the dopant sites allowing a uniform rupture during reset. More interestingly, in oxygen deficient HfO1.5 based devices, intermediate conductance states corresponding to integer or half-integer multiples of quantum conductance (G0) was observed during both the set and reset operations at room temperature. These are related to the better stabilization of intermediate atomic size filament constrictions during the switching process. Occurrence of these intermediate quantum conductance states, especially during the typically abrupt set process, is likely aided by a weaker filament and better thermal dissipation in the highly oxygen deficient devices. These results suggest that a combination of doping and high oxygen vacancy concentration may lead to improved synaptic functionality with concurrent gradual set and reset behaviors

Effect of Annealing Temperature for Ni/AlOx/Pt RRAM Devices Fabricated with Solution-Based Dielectric

Resistive random access memory (RRAM) devices with Ni/AlOx/Pt-structure were manufactured by deposition of a solution-based aluminum oxide (AlOx) dielectric layer which was subsequently annealed at temperatures from 200 °C to 300 °C, in increments of 25 °C. The devices displayed typical bipolar resistive switching characteristics. Investigations were carried out on the effect of different annealing temperatures for associated RRAM devices to show that performance was correlated with changes of hydroxyl group concentration in the AlOx thin films. The annealing temperature of 250 °C was found to be optimal for the dielectric layer, exhibiting superior performance of the RRAM devices with the lowest operation voltage (104), the narrowest resistance distribution, the longest retention time (>104 s) and the most endurance cycles (>150)

On‐Demand Reconfiguration of Nanomaterials: When Electronics Meets Ionics

Rapid advances in the semiconductor industry, driven largely by device scaling, are now approaching fundamental physical limits and face severe power, performance, and cost constraints. Multifunctional materials and devices may lead to a paradigm shift toward new, intelligent, and efficient computing systems, and are being extensively studied. Herein examines how, by controlling the internal ion distribution in a solid‐state film, a material’s chemical composition and physical properties can be reversibly reconfigured using an applied electric field, at room temperature and after device fabrication. Reconfigurability is observed in a wide range of materials, including commonly used dielectric films, and has led to the development of new device concepts such as resistive random‐access memory. Physical reconfigurability further allows memory and logic operations to be merged in the same device for efficient in‐memory computing and neuromorphic computing systems. By directly changing the chemical composition of the material, coupled electrical, optical, and magnetic effects can also be obtained. A survey of recent fundamental material and device studies that reveal the dynamic ionic processes is included, along with discussions on systematic modeling efforts, device and material challenges, and future research directions.By controlling the internal ion distribution in a solid‐state film, the material’s chemical composition and physical (i.e., electrical, optical, and magnetic) properties can be reversibly reconfigured, in situ, using an applied electric field. The reconfigurability is achieved in a wide range of materials, and can lead to the development of new memory, logic, and multifunctional devices and systems.Peer Reviewedhttps://deepblue.lib.umich.edu/bitstream/2027.42/141225/1/adma201702770.pdfhttps://deepblue.lib.umich.edu/bitstream/2027.42/141225/2/adma201702770_am.pd