1,075 research outputs found

    ์ œ์กฐ ์‹œ์Šคํ…œ์—์„œ์˜ ์˜ˆ์ธก ๋ชจ๋ธ๋ง์„ ์œ„ํ•œ ์ง€๋Šฅ์  ๋ฐ์ดํ„ฐ ํš๋“

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    ํ•™์œ„๋…ผ๋ฌธ (๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์‚ฐ์—…๊ณตํ•™๊ณผ, 2021. 2. ์กฐ์„ฑ์ค€.Predictive modeling is a type of supervised learning to find the functional relationship between the input variables and the output variable. Predictive modeling is used in various aspects in manufacturing systems, such as automation of visual inspection, prediction of faulty products, and result estimation of expensive inspection. To build a high-performance predictive model, it is essential to secure high quality data. However, in manufacturing systems, it is practically impossible to acquire enough data of all kinds that are needed for the predictive modeling. There are three main difficulties in the data acquisition in manufacturing systems. First, labeled data always comes with a cost. In many problems, labeling must be done by experienced engineers, which is costly. Second, due to the inspection cost, not all inspections can be performed on all products. Because of time and monetary constraints in the manufacturing system, it is impossible to obtain all the desired inspection results. Third, changes in the manufacturing environment make data acquisition difficult. A change in the manufacturing environment causes a change in the distribution of generated data, making it impossible to obtain enough consistent data. Then, the model have to be trained with a small amount of data. In this dissertation, we overcome this difficulties in data acquisition through active learning, active feature-value acquisition, and domain adaptation. First, we propose an active learning framework to solve the high labeling cost of the wafer map pattern classification. This makes it possible to achieve higher performance with a lower labeling cost. Moreover, the cost efficiency is further improved by incorporating the cluster-level annotation into active learning. For the inspection cost for fault prediction problem, we propose a active inspection framework. By selecting products to undergo high-cost inspection with the novel uncertainty estimation method, high performance can be obtained with low inspection cost. To solve the recipe transition problem that frequently occurs in faulty wafer prediction in semiconductor manufacturing, a domain adaptation methods are used. Through sequential application of unsupervised domain adaptation and semi-supervised domain adaptation, performance degradation due to recipe transition is minimized. Through experiments on real-world data, it was demonstrated that the proposed methodologies can overcome the data acquisition problems in the manufacturing systems and improve the performance of the predictive models.์˜ˆ์ธก ๋ชจ๋ธ๋ง์€ ์ง€๋„ ํ•™์Šต์˜ ์ผ์ข…์œผ๋กœ, ํ•™์Šต ๋ฐ์ดํ„ฐ๋ฅผ ํ†ตํ•ด ์ž…๋ ฅ ๋ณ€์ˆ˜์™€ ์ถœ๋ ฅ ๋ณ€์ˆ˜ ๊ฐ„์˜ ํ•จ์ˆ˜์  ๊ด€๊ณ„๋ฅผ ์ฐพ๋Š” ๊ณผ์ •์ด๋‹ค. ์ด๋Ÿฐ ์˜ˆ์ธก ๋ชจ๋ธ๋ง์€ ์œก์•ˆ ๊ฒ€์‚ฌ ์ž๋™ํ™”, ๋ถˆ๋Ÿ‰ ์ œํ’ˆ ์‚ฌ์ „ ํƒ์ง€, ๊ณ ๋น„์šฉ ๊ฒ€์‚ฌ ๊ฒฐ๊ณผ ์ถ”์ • ๋“ฑ ์ œ์กฐ ์‹œ์Šคํ…œ ์ „๋ฐ˜์— ๊ฑธ์ณ ํ™œ์šฉ๋œ๋‹ค. ๋†’์€ ์„ฑ๋Šฅ์˜ ์˜ˆ์ธก ๋ชจ๋ธ์„ ๋‹ฌ์„ฑํ•˜๊ธฐ ์œ„ํ•ด์„œ๋Š” ์–‘์งˆ์˜ ๋ฐ์ดํ„ฐ๊ฐ€ ํ•„์ˆ˜์ ์ด๋‹ค. ํ•˜์ง€๋งŒ ์ œ์กฐ ์‹œ์Šคํ…œ์—์„œ ์›ํ•˜๋Š” ์ข…๋ฅ˜์˜ ๋ฐ์ดํ„ฐ๋ฅผ ์›ํ•˜๋Š” ๋งŒํผ ํš๋“ํ•˜๋Š” ๊ฒƒ์€ ํ˜„์‹ค์ ์œผ๋กœ ๊ฑฐ์˜ ๋ถˆ๊ฐ€๋Šฅํ•˜๋‹ค. ๋ฐ์ดํ„ฐ ํš๋“์˜ ์–ด๋ ค์›€์€ ํฌ๊ฒŒ ์„ธ๊ฐ€์ง€ ์›์ธ์— ์˜ํ•ด ๋ฐœ์ƒํ•œ๋‹ค. ์ฒซ๋ฒˆ์งธ๋กœ, ๋ผ๋ฒจ๋ง์ด ๋œ ๋ฐ์ดํ„ฐ๋Š” ํ•ญ์ƒ ๋น„์šฉ์„ ์ˆ˜๋ฐ˜ํ•œ๋‹ค๋Š” ์ ์ด๋‹ค. ๋งŽ์€ ๋ฌธ์ œ์—์„œ, ๋ผ๋ฒจ๋ง์€ ์ˆ™๋ จ๋œ ์—”์ง€๋‹ˆ์–ด์— ์˜ํ•ด ์ˆ˜ํ–‰๋˜์–ด์•ผ ํ•˜๊ณ , ์ด๋Š” ํฐ ๋น„์šฉ์„ ๋ฐœ์ƒ์‹œํ‚จ๋‹ค. ๋‘๋ฒˆ์งธ๋กœ, ๊ฒ€์‚ฌ ๋น„์šฉ ๋•Œ๋ฌธ์— ๋ชจ๋“  ๊ฒ€์‚ฌ๊ฐ€ ๋ชจ๋“  ์ œํ’ˆ์— ๋Œ€ํ•ด ์ˆ˜ํ–‰๋  ์ˆ˜ ์—†๋‹ค. ์ œ์กฐ ์‹œ์Šคํ…œ์—๋Š” ์‹œ๊ฐ„์ , ๊ธˆ์ „์  ์ œ์•ฝ์ด ์กด์žฌํ•˜๊ธฐ ๋•Œ๋ฌธ์—, ์›ํ•˜๋Š” ๋ชจ๋“  ๊ฒ€์‚ฌ ๊ฒฐ๊ณผ๊ฐ’์„ ํš๋“ํ•˜๋Š” ๊ฒƒ์ด ์–ด๋ ต๋‹ค. ์„ธ๋ฒˆ์งธ๋กœ, ์ œ์กฐ ํ™˜๊ฒฝ์˜ ๋ณ€ํ™”๊ฐ€ ๋ฐ์ดํ„ฐ ํš๋“์„ ์–ด๋ ต๊ฒŒ ๋งŒ๋“ ๋‹ค. ์ œ์กฐ ํ™˜๊ฒฝ์˜ ๋ณ€ํ™”๋Š” ์ƒ์„ฑ๋˜๋Š” ๋ฐ์ดํ„ฐ์˜ ๋ถ„ํฌ๋ฅผ ๋ณ€ํ˜•์‹œ์ผœ, ์ผ๊ด€์„ฑ ์žˆ๋Š” ๋ฐ์ดํ„ฐ๋ฅผ ์ถฉ๋ถ„ํžˆ ํš๋“ํ•˜์ง€ ๋ชปํ•˜๊ฒŒ ํ•œ๋‹ค. ์ด๋กœ ์ธํ•ด ์ ์€ ์–‘์˜ ๋ฐ์ดํ„ฐ๋งŒ์œผ๋กœ ๋ชจ๋ธ์„ ์žฌํ•™์Šต์‹œ์ผœ์•ผ ํ•˜๋Š” ์ƒํ™ฉ์ด ๋นˆ๋ฒˆํ•˜๊ฒŒ ๋ฐœ์ƒํ•œ๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ์ด๋Ÿฐ ๋ฐ์ดํ„ฐ ํš๋“์˜ ์–ด๋ ค์›€์„ ๊ทน๋ณตํ•˜๊ธฐ ์œ„ํ•ด ๋Šฅ๋™ ํ•™์Šต, ๋Šฅ๋™ ํ”ผ์ณ๊ฐ’ ํš๋“, ๋„๋ฉ”์ธ ์ ์‘ ๋ฐฉ๋ฒ•์„ ํ™œ์šฉํ•œ๋‹ค. ๋จผ์ €, ์›จ์ดํผ ๋งต ํŒจํ„ด ๋ถ„๋ฅ˜ ๋ฌธ์ œ์˜ ๋†’์€ ๋ผ๋ฒจ๋ง ๋น„์šฉ์„ ํ•ด๊ฒฐํ•˜๊ธฐ ์œ„ํ•ด ๋Šฅ๋™ํ•™์Šต ํ”„๋ ˆ์ž„์›Œํฌ๋ฅผ ์ œ์•ˆํ•œ๋‹ค. ์ด๋ฅผ ํ†ตํ•ด ์ ์€ ๋ผ๋ฒจ๋ง ๋น„์šฉ์œผ๋กœ ๋†’์€ ์„ฑ๋Šฅ์˜ ๋ถ„๋ฅ˜ ๋ชจ๋ธ์„ ๊ตฌ์ถ•ํ•  ์ˆ˜ ์žˆ๋‹ค. ๋‚˜์•„๊ฐ€, ๊ตฐ์ง‘ ๋‹จ์œ„์˜ ๋ผ๋ฒจ๋ง ๋ฐฉ๋ฒ•์„ ๋Šฅ๋™ํ•™์Šต์— ์ ‘๋ชฉํ•˜์—ฌ ๋น„์šฉ ํšจ์œจ์„ฑ์„ ํ•œ์ฐจ๋ก€ ๋” ๊ฐœ์„ ํ•œ๋‹ค. ์ œํ’ˆ ๋ถˆ๋Ÿ‰ ์˜ˆ์ธก์— ํ™œ์šฉ๋˜๋Š” ๊ฒ€์‚ฌ ๋น„์šฉ ๋ฌธ์ œ๋ฅผ ํ•ด๊ฒฐํ•˜๊ธฐ ์œ„ํ•ด์„œ๋Š” ๋Šฅ๋™ ๊ฒ€์‚ฌ ๋ฐฉ๋ฒ•์„ ์ œ์•ˆํ•œ๋‹ค. ์ œ์•ˆํ•˜๋Š” ์ƒˆ๋กœ์šด ๋ถˆํ™•์‹ค์„ฑ ์ถ”์ • ๋ฐฉ๋ฒ•์„ ํ†ตํ•ด ๊ณ ๋น„์šฉ ๊ฒ€์‚ฌ ๋Œ€์ƒ ์ œํ’ˆ์„ ์„ ํƒํ•จ์œผ๋กœ์จ ์ ์€ ๊ฒ€์‚ฌ ๋น„์šฉ์œผ๋กœ ๋†’์€ ์„ฑ๋Šฅ์„ ์–ป์„ ์ˆ˜ ์žˆ๋‹ค. ๋ฐ˜๋„์ฒด ์ œ์กฐ์˜ ์›จ์ดํผ ๋ถˆ๋Ÿ‰ ์˜ˆ์ธก์—์„œ ๋นˆ๋ฒˆํ•˜๊ฒŒ ๋ฐœ์ƒํ•˜๋Š” ๋ ˆ์‹œํ”ผ ๋ณ€๊ฒฝ ๋ฌธ์ œ๋ฅผ ํ•ด๊ฒฐํ•˜๊ธฐ ์œ„ํ•ด์„œ๋Š” ๋„๋ฉ”์ธ ์ ์‘ ๋ฐฉ๋ฒ•์„ ํ™œ์šฉํ•œ๋‹ค. ๋น„๊ต์‚ฌ ๋„๋ฉ”์ธ ์ ์‘๊ณผ ๋ฐ˜๊ต์‚ฌ ๋„๋ฉ”์ธ ์ ์‘์˜ ์ˆœ์ฐจ์ ์ธ ์ ์šฉ์„ ํ†ตํ•ด ๋ ˆ์‹œํ”ผ ๋ณ€๊ฒฝ์— ์˜ํ•œ ์„ฑ๋Šฅ ์ €ํ•˜๋ฅผ ์ตœ์†Œํ™”ํ•œ๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ์‹ค์ œ ๋ฐ์ดํ„ฐ์— ๋Œ€ํ•œ ์‹คํ—˜์„ ํ†ตํ•ด ์ œ์•ˆ๋œ ๋ฐฉ๋ฒ•๋ก ๋“ค์ด ์ œ์กฐ์‹œ์Šคํ…œ์˜ ๋ฐ์ดํ„ฐ ํš๋“ ๋ฌธ์ œ๋ฅผ ๊ทน๋ณตํ•˜๊ณ  ์˜ˆ์ธก ๋ชจ๋ธ์˜ ์„ฑ๋Šฅ์„ ๋†’์ผ ์ˆ˜ ์žˆ์Œ์„ ํ™•์ธํ•˜์˜€๋‹ค.1. Introduction 1 2. Literature Review 9 2.1 Review of Related Methodologies 9 2.1.1 Active Learning 9 2.1.2 Active Feature-value Acquisition 11 2.1.3 Domain Adaptation 14 2.2 Review of Predictive Modelings in Manufacturing 15 2.2.1 Wafer Map Pattern Classification 15 2.2.2 Fault Detection and Classification 16 3. Active Learning for Wafer Map Pattern Classification 19 3.1 Problem Description 19 3.2 Proposed Method 21 3.2.1 System overview 21 3.2.2 Prediction model 25 3.2.3 Uncertainty estimation 25 3.2.4 Query wafer selection 29 3.2.5 Query wafer labeling 30 3.2.6 Model update 30 3.3 Experiments 31 3.3.1 Data description 31 3.3.2 Experimental design 31 3.3.3 Results and discussion 34 4. Active Cluster Annotation for Wafer Map Pattern Classification 42 4.1 Problem Description 42 4.2 Proposed Method 44 4.2.1 Clustering of unlabeled data 46 4.2.2 CNN training with labeled data 48 4.2.3 Cluster-level uncertainty estimation 49 4.2.4 Query cluster selection 50 4.2.5 Cluster-level annotation 50 4.3 Experiments 51 4.3.1 Data description 51 4.3.2 Experimental setting 51 4.3.3 Clustering results 53 4.3.4 Classification performance 54 4.3.5 Analysis for label noise 57 5. Active Inspection for Fault Prediction 60 5.1 Problem Description 60 5.2 Proposed Method 65 5.2.1 Active inspection framework 65 5.2.2 Acquisition based on Expected Prediction Change 68 5.3 Experiments 71 5.3.1 Data description 71 5.3.2 Fault prediction models 72 5.3.3 Experimental design 73 5.3.4 Results and discussion 74 6. Adaptive Fault Detection for Recipe Transition 76 6.1 Problem Description 76 6.2 Proposed Method 78 6.2.1 Overview 78 6.2.2 Unsupervised adaptation phase 81 6.2.3 Semi-supervised adaptation phase 83 6.3 Experiments 85 6.3.1 Data description 85 6.3.2 Experimental setting 85 6.3.3 Performance degradation caused by recipe transition 86 6.3.4 Effect of unsupervised adaptation 87 6.3.5 Effect of semi-supervised adaptation 88 7. Conclusion 91 7.1 Contributions 91 7.2 Future work 94Docto

    Doctor of Philosophy

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    dissertationIn order to ensure high production yield of semiconductor devices, it is desirable to characterize intermediate progress towards the final product by using metrology tools to acquire relevant measurements after each sequential processing step. The metrology data are commonly used in feedback and feed-forward loops of Run-to-Run (R2R) controllers to improve process capability and optimize recipes from lot-to-lot or batch-to-batch. In this dissertation, we focus on two related issues. First, we propose a novel non-threaded R2R controller that utilizes all available metrology measurements, even when the data were acquired during prior runs that differed in their contexts from the current fabrication thread. The developed controller is the first known implementation of a non-threaded R2R control strategy that was successfully deployed in the high-volume production semiconductor fab. Its introduction improved the process capability by 8% compared with the traditional threaded R2R control and significantly reduced out of control (OOC) events at one of the most critical steps in NAND memory manufacturing. The second contribution demonstrates the value of developing virtual metrology (VM) estimators using the insight gained from multiphysics models. Unlike the traditional statistical regression techniques, which lead to linear models that depend on a linear combination of the available measurements, we develop VM models, the structure of which and the functional interdependence between their input and output variables are determined from the insight provided by the multiphysics describing the operation of the processing step for which the VM system is being developed. We demonstrate this approach for three different processes, and describe the superior performance of the developed VM systems after their first-of-a-kind deployment in a high-volume semiconductor manufacturing environment

    Virtual metrology for semiconductor manufacturing applications

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    Per essere competitive nel mercato, le industrie di semiconduttori devono poter raggiungere elevati standard di produzione a un prezzo ragionevole. Per motivi legati tanto ai costi quanto ai tempi di esecuzione, una strategia di controllo della qualitร  che preveda la misurazione completa del prodotto non รจ attuabile; i test sono eettuati su un ristretto campione dei dati originali. Il traguardo del presente lavoro di Tesi รจ lo studio e l'implementazione, attraverso metodologie di modellistica tipo non lineare, di un algoritmo di metrologia virtuale (Virtual Metrology) d'ausilio al controllo di processo nella produzione di semiconduttori. Infatti, la conoscenza di una stima delle misure non realmente eseguite (misure virtuali) puรฒ rappresentare un primo passo verso la costruzione di sistemi di controllo di processo e controllo della qualitร  sempre piรน ranati ed ecienti. Da un punto di vista operativo, l'obiettivo รจ fornire la piรน accurata stima possibile delle dimensioni critiche a monte della fase di etching, a partire dai dati disponibili (includendo misurazioni da fasi di litograa e deposizione e dati di processo - ove disponibili). Le tecniche statistiche allo stato dell'arte analizzate in questo lavoro comprendono: - multilayer feedforward networks; Confronto e validazione degli algoritmi presi in esame sono stati possibili grazie ai data-set forniti da un'industria manifatturiera di semiconduttori. In conclusione, questo lavoro di Tesi rappresenta un primo passo verso la creazione di un sistema di controllo di processo e controllo della qualitร  evoluto e essibile, che abbia il ne ultimo di migliorare la qualitร  della produzione.ope

    Nano-optical sensing and metrology through near-to far-field transduction

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    Co-Nanomet: Co-ordination of Nanometrology in Europe

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    Nanometrology is a subfield of metrology, concerned with the science of measurement at the nanoscale level. Todayโ€™s global economy depends on reliable measurements and tests, which are trusted and accepted internationally. It must provide the ability to measure in three dimensions with atomic resolution over large areas. For industrial application this must also be achieved at a suitable speed/throughput. Measurements in the nanometre range should be traceable back to internationally accepted units of measurement (e.g. of length, angle, quantity of matter, and force). This requires common, validated measurement methods, calibrated scientific instrumentation as well as qualified reference samples. In some areas, even a common vocabulary needs to be defined. A traceability chain for the required measurements in the nm range has been established in only a few special cases. A common strategy for European nanometrology has been defined, as captured herein, such that future nanometrology development in Europe may build out from our many current strengths. In this way, European nanotechnology will be supported to reach its full and most exciting potential. As a strategic guidance, this document contains a vision for European nanometrology 2020; future goals and research needs, building out from an evaluation of the status of science and technology in 2010. It incorporates concepts for the acceleration of European nanometrology, in support of the effective commercial exploitation of emerging nanotechnologies. The field of nanotechnology covers a breadth of disciplines, each of which has specific and varying metrological needs. To this end, a set of four core technology fields or priority themes (Engineered Nanoparticles, Nanobiotechnology, Thin Films and Structured Surfaces and Modelling & Simulation) are the focus of this review. Each represents an area within which rapid scientific development during the last decade has seen corresponding growth in or towards commercial exploitation routes. This document was compiled under the European Commission Framework Programme 7 project, Co-Nanomet. It has drawn together input from industry, research institutes, (national) metrology institutes, regulatory and standardisation bodies across Europe. Through the common work of the partners and all those interested parties who have contributed, it represents a significant collaborative European effort in this important field. In the next decade, nanotechnology can be expected to approach maturity, as a major enabling technological discipline with widespread application. This document provides a guide to the many bodies across Europe in their activities or responsibilities in the field of nanotechnology and related measurement requirements. It will support the commercial exploitation of nanotechnology, as it transitions through this next exciting decade

    Reusable modelling and simulation of flexible manufacturing for next generation semiconductor manufacturing facilities

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    Automated material handling systems (AMHS) in 300 mm semiconductor manufacturing facilities may need to evolve faster than expected considering the high performance demands on these facilities. Reusable simulation models are needed to cope with the demands of this dynamic environment and to deliver answers to the industry much faster. One vision for intrabay AMHS is to link a small group of intrabay AMHS systems, within a full manufacturing facility, together using what is called a Merge/Diverge link. This promises better operational performance of the AMHS when compared to operating two dedicated AMHS systems, one for interbay transport and the other for intrabay handling. A generic tool for modelling and simulation of an intrabay AMHS (GTIA-M&S) is built, which utilises a library of different blocks representing the different components of any intrabay material handling system. GTIA-M&S provides a means for rapid building and analysis of an intrabay AMHS under different operating conditions. The ease of use of the tool means that inexpert users have the ability to generate good models. Models developed by the tool can be executed with the merge/diverge capability enabled or disabled to provide comparable solutions to production demands and to compare these two different configurations of intrabay AMHS using a single simulation model. Finally, results from simulation experiments on a model developed using the tool were very informative in that they include useful decision making data, which can now be used to further enhance and update the design and operational characteristics of the intrabay AMHS

    Architectural level delay and leakage power modelling of manufacturing process variation

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    PhD ThesisThe effect of manufacturing process variations has become a major issue regarding the estimation of circuit delay and power dissipation, and will gain more importance in the future as device scaling continues in order to satisfy market place demands for circuits with greater performance and functionality per unit area. Statistical modelling and analysis approaches have been widely used to reflect the effects of a variety of variational process parameters on system performance factor which will be described as probability density functions (PDFs). At present most of the investigations into statistical models has been limited to small circuits such as a logic gate. However, the massive size of present day electronic systems precludes the use of design techniques which consider a system to comprise these basic gates, as this level of design is very inefficient and error prone. This thesis proposes a methodology to bring the effects of process variation from transistor level up to architectural level in terms of circuit delay and leakage power dissipation. Using a first order canonical model and statistical analysis approach, a statistical cell library has been built which comprises not only the basic gate cell models, but also more complex functional blocks such as registers, FIFOs, counters, ALUs etc. Furthermore, other sensitive factors to the overall system performance, such as input signal slope, output load capacitance, different signal switching cases and transition types are also taken into account for each cell in the library, which makes it adaptive to an incremental circuit design. The proposed methodology enables an efficient analysis of process variation effects on system performance with significantly reduced computation time compared to the Monte Carlo simulation approach. As a demonstration vehicle for this technique, the delay and leakage power distributions of a 2-stage asynchronous micropipeline circuit has been simulated using this cell library. The experimental results show that the proposed method can predict the delay and leakage power distribution with less than 5% error and at least 50,000 times faster computation time compare to 5000-sample SPICE based Monte Carlo simulation. The methodology presented here for modelling process variability plays a significant role in Design for Manufacturability (DFM) by quantifying the direct impact of process variations on system performance. The advantages of being able to undertake this analysis at a high level of abstraction and thus early in the design cycle are two fold. First, if the predicted effects of process variation render the circuit performance to be outwith specification, design modifications can be readily incorporated to rectify the situation. Second, knowing what the acceptable limits of process variation are to maintain design performance within its specification, informed choices can be made regarding the implementation technology and manufacturer selected to fabricate the design

    NASA SBIR abstracts of 1991 phase 1 projects

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    The objectives of 301 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1991 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 301, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1991 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included
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