Ta2O5/SiO2 Multicomponent Dielectrics for Amorphous Oxide TFTs

Co-sputtering of SiO2 and high-κ Ta2O5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 °C). Characterization of the multicomponent layers and of the TFTs working characteristics (employing them) was performed in terms of static performance, reliability, and stability to understand the role of the incorporation of the high-κ material in the gate dielectric stack. It is shown that inherent disadvantages of the high-κ material, such as poorer interface properties and poor gate insulation, can be counterbalanced by inclusion of SiO2 both mixed with Ta2O5 and as thin interfacial layers. A stack comprising a (Ta2O5)x(SiO2)100 − x film with x = 69 and a thin SiO2 film at the interface with IGZO resulted in the best performing TFTs, with field-effect mobility (µFE) ≈ 16 cm2·V−1·s−1, subthreshold slope (SS) ≈ 0.15 V/dec and on/off ratio exceeding 107. Anomalous Vth shifts were observed during positive gate bias stress (PGBS), followed by very slow recoveries (time constant exceeding 8 × 105 s), and analysis of the stress and recovery processes for the different gate dielectric stacks showed that the relevant mechanism is not dominated by the interfaces but seems to be related to the migration of charged species in the dielectric. The incorporation of additional SiO2 layers into the gate dielectric stack is shown to effectively counterbalance this anomalous shift. This multilayered gate dielectric stack approach is in line with both the large area and the flexible electronics needs, yielding reliable devices with performance suitable for successful integration on new electronic applications.publishersversionpublishe

PHYSICAL MODELING OF ELECTRICAL AND DIELECTRIC PROPERTIES OF HIGH-k Ta2O5 BASED MOS CAPACITORS ON SILICON

In this paper we present an integral physical model for describing electrical and dielectric properties of MOS structures containing dielectric stack composed of a high-k dielectric (with emphasize on pure and doped Ta2O5) and an interfacial silicon dioxide or silicon oxynitride layer. Based on the model, an equivalent circuit of the structure is proposed. Validity of the model was demonstrated for structures containing different metal gates (Al, Au, Pt, W, TiN, Mo) and different Ta2O5 based high-k dielectrics, grown of bare or nitrided silicon substrates.The model describes very well the I-V characteristics of the considered structures, as well as frequency dependence of the capacitance in accumulation. Stress-induced leakage currents are also effectively analyzed by the use of the model

Study of High-k Dielectrics and their Interfaces on Semiconductors for Device Applications

This thesis has focused on two emerging applications of high-k dielectrics in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and in Metal-InsulatorSemiconductor High Electron Mobility Transistors (MIS-HEMTs). The key aim has been to propose the best routes for passivation of semiconductor/high-k oxide interfaces by investigating the band alignments and interface properties of several oxides, such as Tm2O3, Ta2O5, ZrO2, Al2O3 and MgO, deposited on different semiconductors: Si, Ge, GaN, InGaAs and InGaSb. The electrical characterisation of fabricated MIS capacitor and (MIS)-HEMT devices have also been performed. Thulium silicate (TmSiO) has been identified as a promising candidate for integration as interfacial layer (IL) in HfO2/TiN MOSFETs. The physical properties of Tm2O3/IL/Si interface have been elucidated, where IL (TmSiO) has been formed using different post-deposition annealing (PDA) temperatures, from 550 to 750 °C. It has been found that the best-scaled stack (sub-nm IL) is formed at 550 °C PDA with a graded interface layer and a strong SiOx (Si 3+) component. A large valence band offset (VBO) of 2.8 eV and a large conduction band offset (CBO) of 1.9 eV have been derived for Tm2O3/Si by X-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry. Further increase of device performance can be achieved by replacing Si with GaN for high frequency, high power and high-temperature operation. In this thesis, several GaN cleaning procedures have been considered: 30% NH4OH, 20% (NH4)2S, and 37% HCl. It has been found that the HCl treatment shows the lowest oxygen contamination and Garich surface, and hence has been used prior sputtering of Ta2O5, Al2O3, ZrO2 and MgO on GaN. The large VBOs of 1.1 eV and 1.2 eV have been derived for Al2O3 and MgO on GaN respectively, using XPS and Kraut’s method; the corresponding CBOs are 2.0 eV and 2.8 eV respectively, taking into account the band gaps of Al2O3 (6.5 eV) and MgO (7.4 eV) determined from XPS O 1s electron energy spectra. The lowest leakage currents were obtained for devices with Al2O3 and MgO, i.e. 5.3 ×10-6 A/cm2 and 3.2 ×10-6 A/cm2 at 1 V, respectively in agreement with high band offsets (> 1 eV). Furthermore, the effect of different surface treatments (HCl, O2 plasma and 1-Octadecanethiol (ODT)) prior to atomic layer deposition of Al2O3 on the GaN/AlGaN/GaN heterostructure has been investigated. The MIS-HEMTs fabricated using the low-cost ODT GaN surface treatment have been found to exhibit superior performance for power switching applications such as a low threshold voltage, VT of -12.3 V, hysteresis of 0.12 V, a small subthreshold voltage slope (SS) of 73 mV/dec, and a low density of interface states, Dit of 3.0 x10^12 cm-2eV-1. A comprehensive novel study of HfO2/InGaAs and Al2O3/InGaSb interfaces have also been conducted for use in III-V based MOSFETs. The addition of the plasma H2/TMA/H2 pre-cleaning has been found to be very effective in recovering etch damage on InGaAs, especially for (110) orientation, and led to the improvement of electrical characteristics. Furthermore, the combination of H2 plasma exposure and forming gas anneal yielded significantly improved metrics for Al2O3/InGaSb over the control HCltreated sample, with the 150 W plasma treatment giving both the highest capacitance and the lowest stretch out

HfO2 as gate dielectric on Si and Ge substrate

Hafnium oxide HfO2 has been considered as an alternative to silicon dioxide SiO2 in future nano-scale complementary metal-oxide-semiconductor (CMOS) devices since it provides the required capacitance at the reduced device size because of its high dielectric constant. HfO2 films are currently deposited by various techniques. Many of them require high temperature annealing that can impact device performance and reliability. In this research, electrical characteristics of capacitors with HfO2 as gate dielectric deposited by standard thermal evaporation and e-beam evaporation on Si and Ge substrates were investigated. The dielectric constant of HfO2 deposited by thermal evaporation on Si is in the range of 18-25. Al/HfO2/Si MOS capacitors annealed at 450°C show low hysteresis, leakage current density and bulk oxide charges. Interface state density and low temperature charge trapping behavior of these structures were also investigated. Degradation in surface carrier mobility has been reported in Si field-effect-transistors with HfO2 as gate dielectric. To explore the possibility of alleviating this problem we have used germanium (Ge) substrate as this semiconductor has higher carrier mobility than Si. Devices fabricated by depositing HfO2 directly on Ge by standard thermal evaporation were found to be too leaky and show significant hysteresis and large shift in flatband voltage. This deterioration in electrical performance is mainly due to the formation of unstable interfacial layer of GeO2 during the HfO2 deposition. To minimize this effect, Ge surface was treated with the beam of atomic nitrogen prior to the dielectric deposition. The effect of surface nitridation, on interface as well as on bulk oxide, trap energy levels were investigated using low temperature C-V measurements. They revealed additional defect levels in the nitrided devices indicating diffusion of nitrogen from interface into the bulk oxide. Impact of surface nitridation on the reliability of Ge/HfO2/Al MOS capacitors has been investigated by application of constant voltage stress at different voltage levels for various time periods. It was observed that deeper trap levels in nitrided devices, found from low frequency and low temperature measurements, trap the charge carrier immediately after stress but with time these carriers detrap and create more traps inside the bulk oxide resulting in further devices deterioration. It is inferred that though nitrogen is effective in reducing interfacial layer growth it incorporates more defects at interface as well as in bulk oxide. Therefore, it is important to look into alternative methods of surface passivation to limit the growth of GeO2 at the interface

High-K Dielectrics in Metal Insulator Metal (MIM) Capacitors for RF Applications

Ph.DDOCTOR OF PHILOSOPH

CONSIDERATION OF CONDUCTION MECHANISMS IN HIGH-K DIELECTRIC STACKS AS A TOOL TO STUDY ELECTRICALLY ACTIVE DEFECTS

In this paper conduction mechanisms which could govern the electron transport through high-k dielectrics are summarized. The influence of various factors – the type of high-k dielectric and its thickness; the doping with a certain element; the type of metal electrode as well as the measurement conditions (bias, polarity and temperature), on the leakage currents and dominant conduction mechanisms have been considered. Practical hints how to consider different conduction mechanisms and to differentiate between them are given. The paper presents an approach to assess important trap parameters from investigation of dominant conduction mechanisms

Investigation of high-K gate dielectrics for advanced CMOS application

Ph.DDOCTOR OF PHILOSOPH

Improved Performance of Amorphous InGaZnO Thin-Film Transistor with Ta2O5 Gate Dielectric by using La Incorporation

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Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures