Infrastructures and Algorithms for Testable and Dependable Systems-on-a-Chip

Every new node of semiconductor technologies provides further miniaturization and higher performances, increasing the number of advanced functions that electronic products can offer. Silicon area is now so cheap that industries can integrate in a single chip usually referred to as System-on-Chip (SoC), all the components and functions that historically were placed on a hardware board. Although adding such advanced functionality can benefit users, the manufacturing process is becoming finer and denser, making chips more susceptible to defects. Today’s very deep-submicron semiconductor technologies (0.13 micron and below) have reached susceptibility levels that put conventional semiconductor manufacturing at an impasse. Being able to rapidly develop, manufacture, test, diagnose and verify such complex new chips and products is crucial for the continued success of our economy at-large. This trend is expected to continue at least for the next ten years making possible the design and production of 100 million transistor chips. To speed up the research, the National Technology Roadmap for Semiconductors identified in 1997 a number of major hurdles to be overcome. Some of these hurdles are related to test and dependability. Test is one of the most critical tasks in the semiconductor production process where Integrated Circuits (ICs) are tested several times starting from the wafer probing to the end of production test. Test is not only necessary to assure fault free devices but it also plays a key role in analyzing defects in the manufacturing process. This last point has high relevance since increasing time-to-market pressure on semiconductor fabrication often forces foundries to start volume production on a given semiconductor technology node before reaching the defect densities, and hence yield levels, traditionally obtained at that stage. The feedback derived from test is the only way to analyze and isolate many of the defects in today’s processes and to increase process’s yield. With the increasing need of high quality electronic products, at each new physical assembly level, such as board and system assembly, test is used for debugging, diagnosing and repairing the sub-assemblies in their new environment. Similarly, the increasing reliability, availability and serviceability requirements, lead the users of high-end products performing periodic tests in the field throughout the full life cycle. To allow advancements in each one of the above scaling trends, fundamental changes are expected to emerge in different Integrated Circuits (ICs) realization disciplines such as IC design, packaging and silicon process. These changes have a direct impact on test methods, tools and equipment. Conventional test equipment and methodologies will be inadequate to assure high quality levels. On chip specialized block dedicated to test, usually referred to as Infrastructure IP (Intellectual Property), need to be developed and included in the new complex designs to assure that new chips will be adequately tested, diagnosed, measured, debugged and even sometimes repaired. In this thesis, some of the scaling trends in designing new complex SoCs will be analyzed one at a time, observing their implications on test and identifying the key hurdles/challenges to be addressed. The goal of the remaining of the thesis is the presentation of possible solutions. It is not sufficient to address just one of the challenges; all must be met at the same time to fulfill the market requirements

LiDAR aided simulation pipeline for wireless communication in vehicular traffic scenarios

Abstract. Integrated Sensing and Communication (ISAC) is a modern technology under development for Sixth Generation (6G) systems. This thesis focuses on creating a simulation pipeline for dynamic vehicular traffic scenarios and a novel approach to reducing wireless communication overhead with a Light Detection and Ranging (LiDAR) based system. The simulation pipeline can be used to generate data sets for numerous problems. Additionally, the developed error model for vehicle detection algorithms can be used to identify LiDAR performance with respect to different parameters like LiDAR height, range, and laser point density. LiDAR behavior on traffic environment is provided as part of the results in this study. A periodic beam index map is developed by capturing antenna azimuth and elevation angles, which denote maximum Reference Signal Receive Power (RSRP) for a simulated receiver grid on the road and classifying areas using Support Vector Machine (SVM) algorithm to reduce the number of Synchronization Signal Blocks (SSBs) that are needed to be sent in Vehicle to Infrastructure (V2I) communication. This approach effectively reduces the wireless communication overhead in V2I communication

Feasibility study and emulation of the Hough Transform algorithm on FPGA devices for ATLAS Phase-II trigger upgrade

In the next 10 years, a radical upgrade is expected for the Large Hadron Collider focused in achieving the highest values in the instantaneous and integrated luminosity. Both the subdetectrors of the experiments and their data acquisition systems will need an upgrade. For the Phase-II upgrade of the Trigger and Data Acquisition System (TDAQ) of the ATLAS experiment a common platform has been created to share the common firmware, software and tools that are ongoing and that will come in the next years within the ATLAS TDAQ collaboration. The environment includes a set of design procedures, a virtual machine as repository for the firmware and some automatic tools for the continuous integration and versioning. The platform is under testing, as the firmware will be tested on the TDAQ upgraded, it will also be used for the prototype cards that will be produced as demonstrator for the ATLAS Hardware Tracking for the Trigger (HTT) system. For the HTT project a physical environment is being prepared, exploiting Peripheral Component Interconnect express (PCIe) and ACTA crates. My personal work has been the design of a part of track-fitting algorithms, in particular the one using the Hough Transform. This implementation has been required by the ATLAS experiment as an alternative solution to the baseline proposal accepted and described in the TDAQ Upgrade Technical Design Report (TDR). I have developed and tested a set of pattern vectors used not only in the simulation and validation of the algorithm, but also in the hadware integration on a FPGA based hardware accelerator. The used technology is based on high-performance Xilinx Ultrascale+ FPGA, implemented on VCU1525 board. This work is going to be validated by the ATLAS collaboration very soon, so to understand how we can proceed in the future upgrade. Bologna is the only Italian institute which participates in the integration of a tracking algorithm in the ATLAS trigger upgrade, using high performance FPGA-based hardware

Contextual cropping and scaling of TV productions

This is the author's accepted manuscript. The final publication is available at Springer via http://dx.doi.org/10.1007/s11042-011-0804-3. Copyright @ Springer Science+Business Media, LLC 2011.In this paper, an application is presented which automatically adapts SDTV (Standard Definition Television) sports productions to smaller displays through intelligent cropping and scaling. It crops regions of interest of sports productions based on a smart combination of production metadata and systematic video analysis methods. This approach allows a context-based composition of cropped images. It provides a differentiation between the original SD version of the production and the processed one adapted to the requirements for mobile TV. The system has been comprehensively evaluated by comparing the outcome of the proposed method with manually and statically cropped versions, as well as with non-cropped versions. Envisaged is the integration of the tool in post-production and live workflows

The ABC130 barrel module prototyping programme for the ATLAS strip tracker

For the Phase-II Upgrade of the ATLAS Detector, its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100 % silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: an early program using readout chips designed using a 250 nm fabrication process (ABCN-25) and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests.Comment: 82 pages, 66 figure

3D Reconstruction of Building Rooftop and Power Line Models in Right-of-Ways Using Airborne LiDAR Data

The research objectives aimed to achieve thorough the thesis are to develop methods for reconstructing models of building and PL objects of interest in the power line (PL) corridor area from airborne LiDAR data. For this, it is mainly concerned with the model selection problem for which model is more optimal in representing the given data set. This means that the parametric relations and geometry of object shapes are unknowns and optimally determined by the verification of hypothetical models. Therefore, the proposed method achieves high adaptability to the complex geometric forms of building and PL objects. For the building modeling, the method of implicit geometric regularization is proposed to rectify noisy building outline vectors which are due to noisy data. A cost function for the regularization process is designed based on Minimum Description Length (MDL) theory, which favours smaller deviation between a model and observation as well as orthogonal and parallel properties between polylines. Next, a new approach, called Piecewise Model Growing (PMG), is proposed for 3D PL model reconstruction using a catenary curve model. It piece-wisely grows to capture all PL points of interest and thus produces a full PL 3D model. However, the proposed method is limited to the PL scene complexity, which causes PL modeling errors such as partial, under- and over-modeling errors. To correct the incompletion of PL models, the inner and across span analysis are carried out, which leads to replace erroneous PL segments by precise PL models. The inner span analysis is performed based on the MDL theory to correct under- and over-modeling errors. The across span analysis is subsequently carried out to correct partial-modeling errors by finding start and end positions of PLs which denotes Point Of Attachment (POA). As a result, this thesis addresses not only geometrically describing building and PL objects but also dealing with noisy data which causes the incompletion of models. In the practical aspects, the results of building and PL modeling should be essential to effectively analyze a PL scene and quickly alleviate the potentially hazardous scenarios jeopardizing the PL system

Systematic gripper arrangement for a handling device in lightweight production processes

Handhabungsgeräte sind ein integraler Bestandteil automatisierter Produktionsprozesse. Dennoch werden sie in der Regel als nicht wertschöpfend angesehen, weshalb ihre Planung und Projektierung mit geringem Zeit- und Personalaufwand so effektiv wie möglich sein sollte. Gleichzeitig bleiben sie ein wichtiger Teil der Prozesskette und müssen in diesem Zusammenhang bestimmte Bedingungen erfüllen. Um ihre Funktionalität zu gewährleisten und wenig Zeit in die Projektierung zu investieren, sind Handhabungsgeräte oft überdimensioniert. Insbesondere bei flachen Teilen führt dies zu schweren Handhabungslösungen, bei denen das Gewicht des Handhabungsobjekts und des Handhabungsgerätes in einem Missverhältnis zueinander stehen. Ziel der vorliegenden Arbeit ist es, die Projektierung von Handhabungsgeräten so weit wie möglich zu automatisieren. Dieser Prozess wird am Beispiel der Prozesskette zur Herstellung von Leichtbauteilen mit den Verfahren „sheet molding compound“ (SMC) und „resin transfer molding“ (RTM) dargestellt. In einem ersten Schritt wird ein modulares Handhabungsgerät entwickelt und aufgebaut, das eine große Anzahl von Greiferanordnung ermöglicht. Mit diesem Handhabungsgerät kann dann die resultierende Durchbiegung von flachen Bauteilen mit verschiedenen Greiferanordnungen gemessen werden. Um sicherzustellen, dass es nicht immer notwendig ist die Durchbiegungen zu messen, wird mit ABAQUS ein Modell aufgebaut, das eine Simulation der Durchbiegung ermöglicht. Anhand dieses Simulationsmodells wird eine Designlogik für die Anordnung der Greifer entwickelt. Diese Designlogik arbeitet in zwei Schritten und basiert auf dem Ansatz des „growing neural gas“ (GNG), das durch die Implementierung zusätzlicher Regeln an das Problem angepasst wird. Zuerst wird eine erste Greiferkonfiguration basierend auf der Geometrie des Objekts erstellt, die dann durch einen iterativen Prozess aus Simulation und Anpassung verbessert wird. Da die Herstellung von Leichtbauteilen oft mehr als nur einen Zuschnitt erfordert, werden am Ende systematisch verschiedene Lösungen für die verschiedenen Zuschnitte zu einer Greiferanordnung zusammengefasst und ein Verfahren gezeigt, wie dies ,mit dem zuvor entwickelten modularen Handhabungsgerät realisiert, werden kann