753 research outputs found
Amplifier Nonlinear Modeling with RF Pulses
This paper proposes a Volterra kernel identification procedure for wireless amplifiers with nonlinear memory. The technique is based on a reduced-order Volterra model for wideband amplifiers that is favorably compared with widely used memory polynomial model in terms of normalized mean square error. The identification method takes advantage of the particular model structure and is thoroughly derived with a proper selection of pulse-like waveforms of known amplitude as probing signals with special emphasis on the extraction of the fifth-order kernel. The main advantage of the method is that it allows exploring the dynamic range of the amplifier without rising the temperature in the device or altering the biasing point. For validation purposes, a commercial amplifier has been characterized and the extracted kernels have been used to predict the response under wideband code-division multiple-access-like signals. In addition to the simplicity of the deterministic approach used in this extraction procedure, the agreement of the predicted responses with measurements was highly satisfactory in all cases and permitted the capture of phenomena that are due to nonlinear memory effects.CICYT TEC2004-06451-C05-03Junta de Andalucía Grant P07-TIC-0264
Compact Digital Predistortion for Multi-band and Wide-band RF Transmitters
This thesis is focusing on developing a compact digital predistortion (DPD) system
which costs less DPD added power consumptions. It explores a new theory
and techniques to relieve the requirement of the number of training samples and
the sampling-rate of feedback ADCs in DPD systems. A new theory about the
information carried by training samples is introduced. It connects the generalized
error of the DPD estimation algorithm with the statistical properties of
modulated signals. Secondly, based on the proposed theory, this work introduces
a compressed sample selection method to reduce the number of training samples
by only selecting the minimal samples which satisfy the foreknown probability
information. The number of training samples and complex multiplication operations
required for coefficients estimation can be reduced by more than ten
times without additional calculation resource. Thirdly, based on the proposed
theory, this thesis proves that theoretically a DPD system using memory polynomial
based behavioural modes and least-square (LS) based algorithms can be
performed with any sampling-rate of feedback samples. The principle, implementation
and practical concerns of the undersampling DPD which uses lower
sampling-rate ADC are then introduced. Finally, the observation bandwidth of
DPD systems can be extended by the proposed multi-rate track-and-hold circuits
with the associated algorithm. By addressing several parameters of ADC
and corresponding DPD algorithm, multi-GHz observation bandwidth using only
a 61.44MHz ADC is achieved, and demonstrated the satisfactory linearization
performance of multi-band and continued wideband RF transmitter applications
via extensive experimental tests
Constraint-driven RF test stimulus generation and built-in test
With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control.
RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs.
In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead.
Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows:
Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time.
Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test.
Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures
Linear Operation of Switch-Mode Outphasing Power Amplifiers
Radio transceivers are playing an increasingly important role in modern society. The
”connected” lifestyle has been enabled by modern wireless communications. The demand
that has been placed on current wireless and cellular infrastructure requires increased spectral
efficiency however this has come at the cost of power efficiency. This work investigates
methods of improving wireless transceiver efficiency by enabling more efficient power
amplifier architectures, specifically examining the role of switch-mode power amplifiers in
macro cell scenarios. Our research focuses on the mechanisms within outphasing power
amplifiers which prevent linear amplification. From the analysis it was clear that high power
non-linear effects are correctable with currently available techniques however non-linear effects
around the zero crossing point are not. As a result signal processing techniques for suppressing
and avoiding non-linear operation in low power regions are explored. A novel method of digital
pre-distortion is presented, and conventional techniques for linearisation are adapted for the
particular needs of the outphasing power amplifier. More unconventional signal processing
techniques are presented to aid linearisation of the outphasing power amplifier, both zero
crossing and bandwidth expansion reduction methods are designed to avoid operation in nonlinear
regions of the amplifiers. In combination with digital pre-distortion the techniques
will improve linearisation efforts on outphasing systems with dynamic range and bandwidth
constraints respectively.
Our collaboration with NXP provided access to a digital outphasing power amplifier,
enabling empirical analysis of non-linear behaviour and comparative analysis of behavioural
modelling and linearisation efforts. The collaboration resulted in a bench mark for linear
wideband operation of a digital outphasing power amplifier. The complimentary linearisation
techniques, bandwidth expansion reduction and zero crossing reduction have been evaluated in
both simulated and practical outphasing test benches. Initial results are promising and indicate
that the benefits they provide are not limited to the outphasing amplifier architecture alone.
Overall this thesis presents innovative analysis of the distortion mechanisms of the
outphasing power amplifier, highlighting the sensitivity of the system to environmental effects.
Practical and novel linearisation techniques are presented, with a focus on enabling wide band
operation for modern communications standards
Dirty RF Signal Processing for Mitigation of Receiver Front-end Non-linearity
Moderne drahtlose Kommunikationssysteme stellen hohe und teilweise
gegensätzliche Anforderungen an die Hardware der Funkmodule, wie z.B.
niedriger Energieverbrauch, große Bandbreite und hohe Linearität. Die
Gewährleistung einer ausreichenden Linearität ist, neben anderen analogen
Parametern, eine Herausforderung im praktischen Design der Funkmodule. Der
Fokus der Dissertation liegt auf breitbandigen HF-Frontends für
Software-konfigurierbare Funkmodule, die seit einigen Jahren kommerziell
verfügbar sind. Die praktischen Herausforderungen und Grenzen solcher
flexiblen Funkmodule offenbaren sich vor allem im realen Experiment. Eines
der Hauptprobleme ist die Sicherstellung einer ausreichenden analogen
Performanz über einen weiten Frequenzbereich. Aus einer Vielzahl an
analogen Störeffekten behandelt die Arbeit die Analyse und Minderung von
Nichtlinearitäten in Empfängern mit direkt-umsetzender Architektur. Im
Vordergrund stehen dabei Signalverarbeitungsstrategien zur Minderung
nichtlinear verursachter Interferenz - ein Algorithmus, der besser unter
"Dirty RF"-Techniken bekannt ist. Ein digitales Verfahren nach der
Vorwärtskopplung wird durch intensive Simulationen, Messungen und
Implementierung in realer Hardware verifiziert. Um die Lücken zwischen
Theorie und praktischer Anwendbarkeit zu schließen und das Verfahren in
reale Funkmodule zu integrieren, werden verschiedene Untersuchungen
durchgeführt. Hierzu wird ein erweitertes Verhaltensmodell entwickelt, das
die Struktur direkt-umsetzender Empfänger am besten nachbildet und damit
alle Verzerrungen im HF- und Basisband erfasst. Darüber hinaus wird die
Leistungsfähigkeit des Algorithmus unter realen Funkkanal-Bedingungen
untersucht. Zusätzlich folgt die Vorstellung einer ressourceneffizienten
Echtzeit-Implementierung des Verfahrens auf einem FPGA. Abschließend
diskutiert die Arbeit verschiedene Anwendungsfelder, darunter spektrales
Sensing, robuster GSM-Empfang und GSM-basiertes Passivradar. Es wird
gezeigt, dass nichtlineare Verzerrungen erfolgreich in der digitalen
Domäne gemindert werden können, wodurch die Bitfehlerrate gestörter
modulierter Signale sinkt und der Anteil nichtlinear verursachter
Interferenz minimiert wird. Schließlich kann durch das Verfahren die
effektive Linearität des HF-Frontends stark erhöht werden. Damit wird der
zuverlässige Betrieb eines einfachen Funkmoduls unter dem Einfluss der
Empfängernichtlinearität möglich. Aufgrund des flexiblen Designs ist der
Algorithmus für breitbandige Empfänger universal einsetzbar und ist nicht
auf Software-konfigurierbare Funkmodule beschränkt.Today's wireless communication systems place high requirements on the
radio's hardware that are largely mutually exclusive, such as low power
consumption, wide bandwidth, and high linearity. Achieving a sufficient
linearity, among other analogue characteristics, is a challenging issue in
practical transceiver design. The focus of this thesis is on wideband
receiver RF front-ends for software defined radio technology, which became
commercially available in the recent years. Practical challenges and
limitations are being revealed in real-world experiments with these radios.
One of the main problems is to ensure a sufficient RF performance of the
front-end over a wide bandwidth. The thesis covers the analysis and
mitigation of receiver non-linearity of typical direct-conversion receiver
architectures, among other RF impairments. The main focus is on DSP-based
algorithms for mitigating non-linearly induced interference, an approach
also known as "Dirty RF" signal processing techniques. The conceived
digital feedforward mitigation algorithm is verified through extensive
simulations, RF measurements, and implementation in real hardware. Various
studies are carried out that bridge the gap between theory and practical
applicability of this approach, especially with the aim of integrating that
technique into real devices. To this end, an advanced baseband behavioural
model is developed that matches to direct-conversion receiver architectures
as close as possible, and thus considers all generated distortions at RF
and baseband. In addition, the algorithm's performance is verified under
challenging fading conditions. Moreover, the thesis presents a
resource-efficient real-time implementation of the proposed solution on an
FPGA. Finally, different use cases are covered in the thesis that includes
spectrum monitoring or sensing, GSM downlink reception, and GSM-based
passive radar. It is shown that non-linear distortions can be successfully
mitigated at system level in the digital domain, thereby decreasing the bit
error rate of distorted modulated signals and reducing the amount of
non-linearly induced interference. Finally, the effective linearity of the
front-end is increased substantially. Thus, the proper operation of a
low-cost radio under presence of receiver non-linearity is possible. Due to
the flexible design, the algorithm is generally applicable for wideband
receivers and is not restricted to software defined radios
Characterization and modelling of software defined radio front-ends
Doutoramento em Engenharia ElectrotécnicaO presente trabalho tem por objectivo estudar a caracterização e modelação
de arquitecturas de rádio frequência para aplicações em rádios definidos por
software e rádios cognitivos. O constante aparecimento no mercado de novos
padrões e tecnologias para comunicações sem fios têm levantado algumas
limitações à implementação de transceptores rádio de banda larga. Para além
disso, o uso de sistemas reconfiguráveis e adaptáveis baseados no conceito
de rádio definido por software e rádio cognitivo assegurará a evolução para a
próxima geração de comunicações sem fios. A ideia base desta tese passa por
resolver alguns problemas em aberto e propor avanços relevantes, tirando
para isso partido das capacidades providenciadas pelos processadores digitais
de sinal de forma a melhorar o desempenho global dos sistemas propostos.
Inicialmente, serão abordadas várias estratégias para a implementação e
projecto de transceptores rádio, concentrando-se sempre na aplicabilidade
específica a sistemas de rádio definido por software e rádio cognitivo. Serão
também discutidas soluções actuais de instrumentação capaz de caracterizar
um dispositivo que opere simultaneamente nos domínios analógico e digital,
bem como, os próximos passos nesta área de caracterização e modelação.
Além disso, iremos apresentar novos formatos de modelos comportamentais
construídos especificamente para a descrição e caracterização não-linear de
receptores de amostragem passa-banda, bem como, para sistemas nãolineares
que utilizem sinais multi-portadora.
Será apresentada uma nova arquitectura suportada na avaliação estatística
dos sinais rádio que permite aumentar a gama dinâmica do receptor em
situações de multi-portadora. Da mesma forma, será apresentada uma técnica
de maximização da largura de banda de recepção baseada na utilização do
receptor de amostragem passa-banda no formato complexo.
Finalmente, importa referir que todas as arquitecturas propostas serão
acompanhadas por uma introdução teórica e simulações, sempre que possível,
sendo após isto validadas experimentalmente por protótipos laboratoriais.This work investigates the characterization and modeling of radio frequency
front-ends for software defined radio and cognitive radio applications. The
emergence of new standards and technologies in the wireless communications
market are raising several issues to the implementation of wideband
transceiver systems. Also, reconfigurable and adaptable systems based on
software defined and cognitive radio models are paving the way for the next
generation of wireless systems. In this doctoral thesis the fundamental idea is
to address the particular open issues and propose appropriate advancements
by exploring and taking profit from new capabilities of digital signal processors
in a way to improve the overall performance of the novel schemes.
Receiver and transmitter strategies for radio communications are summarized
by concentrating on the usability for software defined radio and cognitive radio
systems. Available instrumentation and next steps for analog and digital radio
frequency hardware characterization is also discussed.
Wideband behavioral model formats are proposed for nonlinear description and
characterization of bandpass sampling receivers, as well as, for multi-carrier
nonlinear systems operation. The proposed models share a great flexibility and
have the freedom to be simply expanded to other fields.
A new design for receiver dynamic range improvement in multi-carrier
scenarios is proposed, which is supported on the useful wireless signals
statistical evaluation. Additionally, receiver-side bandwidth maximization based
on higher-order bandpass sampling approaches is evaluated.
All the proposed designs and modeling strategies are accompanied by
theoretical backgrounds and simulations whenever possible, being then
experimentally validated by laboratory prototypes
Digital Front-End Signal Processing with Widely-Linear Signal Models in Radio Devices
Necessitated by the demand for ever higher data rates, modern communications waveforms have increasingly wider bandwidths and higher signal dynamics. Furthermore, radio devices are expected to transmit and receive a growing number of different waveforms from cellular networks, wireless local area networks, wireless personal area networks, positioning and navigation systems, as well as broadcast systems. On the other hand, commercial wireless devices are expected to be cheap, be relatively small in size, and have a long battery life.
The demands for flexibility and higher data rates on one hand, and the constraints on production cost, device size, and energy efficiency on the other, pose difficult challenges on the design and implementation of future radio transceivers. Under these diametric constraints, in order to keep the overall implementation cost and size feasible, the use of simplified radio architectures and relatively low-cost radio electronics are necessary. This notion is even more relevant for multiple antenna systems, where each antenna has a dedicated radio front-end. The combination of simplified radio front-ends and low-cost electronics implies that various nonidealities in the remaining analog radio frequency (RF) modules, stemming from unavoidable physical limitations and material variations of the used electronics, are expected to play a critical role in these devices. Instead of tightening the specifications and tolerances of the analog circuits themselves, a more cost-effective solution in many cases is to compensate for these nonidealities in the digital domain. This line of research has been gaining increasing interest in the last 10-15 years, and is also the main topic area of this work.
The direct-conversion radio principle is the current and future choice for building low-cost but flexible, multi-standard radio transmitters and receivers. The direct-conversion radio, while simple in structure and integrable on a single chip, suffers from several performance degrading circuit impairments, which have historically prevented its use in wideband, high-rate, and multi-user systems. In the last 15 years, with advances in integrated circuit technologies and digital signal processing, the direct-conversion principle has started gaining popularity. Still, however, much work is needed to fully realize the potential of the direct-conversion principle.
This thesis deals with the analysis and digital mitigation of the implementation nonidealities of direct-conversion transmitters and receivers. The contributions can be divided into three parts. First, techniques are proposed for the joint estimation and predistortion of in-phase/quadrature-phase (I/Q) imbalance, power amplifier (PA) nonlinearity, and local oscillator (LO) leakage in wideband direct-conversion transmitters. Second, methods are developed for estimation and compensation of I/Q imbalance in wideband direct-conversion receivers, based on second-order statistics of the received communication waveforms. Third, these second-order statistics are analyzed for second-order stationary and cyclostationary signals under several other system impairments related to circuit implementation and the radio channel. This analysis brings new insights on I/Q imbalances and their compensation using the proposed algorithms. The proposed algorithms utilize complex-valued signal processing throughout, and naturally assume a widely-linear form, where both the signal and its complex-conjugate are filtered and then summed. The compensation processing is situated in the digital front-end of the transceiver, as the last step before digital-to-analog conversion in transmitters, or in receivers, as the first step after analog-to-digital conversion.
The compensation techniques proposed herein have several common, unique, attributes: they are designed for the compensation of frequency-dependent impairments, which is seen critical for future wideband systems; they require no dedicated training data for learning; the estimators are computationally efficient, relying on simple signal models, gradient-like learning rules, and solving sets of linear equations; they can be applied in any transceiver type that utilizes the direct-conversion principle, whether single-user or multi-user, or single-carrier or multi-carrier; they are modulation, waveform, and standard independent; they can also be applied in multi-antenna transceivers to each antenna subsystem separately. Therefore, the proposed techniques provide practical and effective solutions to real-life circuit implementation problems of modern communications transceivers. Altogether, considering the algorithm developments with the extensive experimental results performed to verify their functionality, this thesis builds strong confidence that low-complexity digital compensation of analog circuit impairments is indeed applicable and efficient
Minimum power design of RF front ends
This thesis describes an investigation into the design of RF front ends with minimum power dissipation. The central question is: "What are the fundamental limits for the power dissipation of telecommunication front ends, and what design procedures can be followed that approach these limits and, at the same time, result in practical circuits?" After a discussion of the state of the art in this area, the elementary operations of a front end are identified. For each of these elementary operations, the fundamental limits for the power dissipation are discussed, divided into technology imposed limits and physics imposed limits. A traditional DECT front end design is used to demonstrate the large difference between the fundamental limits and the power dissipation of existing circuits. To improve this situation, first the optimum distribution of specifications across individual subcircuits needs to be determined, such that the requirements for a specific system can be fulfilled. This is achieved through the introduction of formal transforms of the specifications of subcircuits, which correspond with transforms of the subcircuit itself. Using these transforms, the optimum distribution of gain, noise, linearity and power dissipation can be determined. As it turns out, this optimum distribution can even be represented by a simple, analytical expression. This expression predicts that the power dissipation of the DECT front end can be reduced by a factor of 2.7 through an optimum distribution of the specifications. Using these optimum specifications of the subcircuits, the boundaries for further power dissipation reduction can be determined. This is investigated at the system, circuit and technology level. These insights are used in the design of a 2.5GHz wireless local area network, implemented in an optimized technology ("Silicon on Anything"). The power dissipation of the complete receiver is 3.5mW, more than an order of magnitude below other wireless LAN receivers in recent publications. Finally, the combination of this minimum power design method with a platform based development strategy is discussed
Real-Time FPGA-Based Testbed for Evaluating Digital Predistortion in Fully Digital MIMO Transmitters
As one of the key enabling technologies of 5G networks, massive multiple-input, multiple-output (MIMO) transmitters use many transmit chains to ensure a very high data rate and acceptable signal quality. Realizing Massive MIMO not only includes increasing antenna count but also requires proportionally more power amplifiers (PAs). Digital predistortion (DPD) is a well-established signal processing method that mitigates the non-linearities of a PA when operated near saturation. Design tradeoffs must be carefully considered to reduce the system's overall power requirements given the high PA count in MIMO systems. This implies DPD power consumption for each transmission chain must be minimized. Apart from this, larger transmission bandwidths in next-generation networks require high hardware clock rates on the order of a few gigahertz. Current hardware can satisfy clock rates of up to hundreds of megahertz. Thus, there is a need for parallelized signal processing methods to meet bandwidth requirements.
This thesis investigates and addresses some challenges for deploying massive MIMO systems by designing and building a reconfigurable digital signal processing (DSP) testbed that allows for the implementation and validation of real-time DSP algorithms including DPD, for fully digital massive MIMO transceivers. This testbed allows transmission of up to 16 fully digital transmission chains at sub-6 GHz frequencies and supports up to 120 MHz of modulation bandwidths. Finally, a low-complexity and parallelized piecewise-linear (PWL) dual-input dual-output (DISO) DPD solution is proposed for linearizing MIMO transmitters. This DPD solution is realized with a commercially available field-programmable-gate-array (FPGA)
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