Processing-structure-protrusion relationship of 3D Cu TSVs: control at the atomic scale

A phase-field-crystal model is used to investigate the processing-structure-protrusion relationship of blind Cu through-silicon vias (TSVs) at the atomic scale. A higher temperature results in a larger TSV protrusion. Deformation via dislocation motion dominates at temperatures lower than around 300∘C, while both diffusional and dislocation creep occur at temperatures greater than around 300∘C. TSVs with smaller sidewall roughness Ra and wavelength λa exhibit larger protrusions. Moreover, different protrusion profiles are observed for TSVs with different grain structures. Both protrusions and intrusions are observed when a single grain is placed near the TSV top end, while the top surface protrudes near both edges when it contains more grains. Under symmetric loading, coalescence of the grains occurs near the top end, and a symmetric grain structure can accelerate this process. The strain distributions in TSVs are calculated, and the eigenstrain projection along the vertical direction can be considered an index to predict the TSV protrusion tendency

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Cu Protrusion of Different through-Silicon via Shapes under Annealing Process

The through-silicon via (TSV) 3D integration method has become one of the most widely used techniques for achieving system-level integration for applications that require smaller package sizes, higher interconnection density and high performance. This is because the TSV fabrication technology provides the mechanism for facilitating communications between various layers of the 3D integration system and for interconnecting stacked devices at wafer-level. Although there are several reported studies on TSV 3D integration R&D, with most of these studies focused on the improvement of TSV fabrication process, there are very limited in-depth studies associated with the TSV reliability issues and challenges. In this paper, we investigate the effect of TSV geometries on the associated TSV reliability factors. Different TSV geometries including I-type, tapered, elliptical, triangular, quadrangular and circular shapes (with same volume) are investigated to find the most reliable structure under annealing process. The results show that the tapered TSV shape releases thermo-mechanical stress more uniformly than other shapes and larger top surface shows better reliability

Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam System

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XL

Enabling Technologies for 3D ICs: TSV Modeling and Analysis

Through silicon via (TSV) based three-dimensional (3D) integrated circuit (IC) aims to stack and interconnect dies or wafers vertically. This emerging technology offers a promising near-term solution for further miniaturization and the performance improvement of electronic systems and follows a more than Moore strategy. Along with the need for low-cost and high-yield process technology, the successful application of TSV technology requires further optimization of the TSV electrical modeling and design. In the millimeter wave (mmW) frequency range, the root mean square (rms) height of the TSV sidewall roughness is comparable to the skin depth and hence becomes a critical factor for TSV modeling and analysis. The impact of TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed following the second order small perturbation method. Then, an accurate and efficient electrical model for TSVs has been proposed considering the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor (MOS) effect. However, the emerging application of 3D integration involves an advanced bio-inspired computing system which is currently experiencing an explosion of interest. In neuromorphic computing, the high density membrane capacitor plays a key role in the synaptic signaling process, especially in a spike firing analog implementation of neurons. We proposed a novel 3D neuromorphic design architecture in which the redundant and dummy TSVs are reconfigured as membrane capacitors. This modification has been achieved by taking advantage of the metal insulator semiconductor (MIS) structure along the sidewall, strategically engineering the fixed oxide charges in depletion region surrounding the TSVs, and the addition of oxide layer around the bump without changing any process technology. Without increasing the circuit area, these reconfiguration of TSVs can result in substantial power consumption reduction and a significant boost to chip performance and efficiency. Also, depending on the availability of the TSVs, we proposed a novel CAD framework for TSV assignments based on the force-directed optimization and linear perturbation

Electrical characterization of plasma-enhanced Cvd silicon nitride dielectric on copper

In this work, a novel metal-insulator-metal (MIM) capacitor process is introduced and integrated in a Copper Interconnect technology, whose smallest feature size is 0.18mum process, which has good yield, reliability and repeatability. The MIM uses a one-photomask process and hence is termed as the Low-cost-integration (LCI) MIM. The LCI MIM uses copper as the bottom electrode, plasma enhanced silicon nitride as the dielectric, and Tantalum nitride as the top electrode. The target capacitance density is 1.5fF/mum2. The target leakage current is 1e-7A/cm2 at 3.3V at 125°C. The maximum operating voltages that the MIM is designed for is 5V. The voltage linearity is desired to be less than 100ppm/v; The purpose of the study is to determine the feasibility of integrating the low-cost-integration (LCI) MIM capacitor and to characterize the device to ensure that it meets the above mentioned target values for the various parameters. This is done by electrically characterizing the capacitor for the capacitance change with voltage, the leakage current at accelerated voltages and the time-dependent-dielectric breakdown (TDDB) under various electric fields. (Abstract shortened by UMI.)

Thermo-Mechanical Effects Of Thermal Cycled Copper Through Silicon Vias

The semiconductor industry is currently facing transistor scaling issues due to fabrication thresholds and quantum effects. In this \u27More-Than-Moore\u27 era, the industry is developing new ways to increase device performance, such as stacking chips for three-dimensional integrated circuits (3D-IC). The 3D-IC\u27s superior performance over their 2D counterparts can be attributed to the use of vertical interconnects, or through silicon vias (TSV). These interconnects are much shorter, reducing signal delay. However TSVs are susceptible to various thermo-mechanical reliability concerns. Heating during fabrication and use, in conjunction with coefficient of thermal expansion mismatch between the copper TSVs and silicon substrate, create harmful stresses in the system. The purpose of this work is to evaluate the signal integrity of Cu-TSVs and determine the major contributing factors of the signal degradation upon in-use conditions. Two series of samples containing blind Cu-TSVs embedded in a Si substrate were studied, each having different types and amounts of voids from manufacturing. The samples were thermally cycled up to 2000 times using three maximum temperatures to simulate three unique in-use conditions. S11 parameter measurements were then conducted to determine the signal integrity of the TSVs. To investigate the internal response from cycling, a protocol was developed for cross-sectioning the copper TSVs. Voids were measured using scanning electron microscope and focused ion beam imaging of the cross-sections, while the microstructural evolution of the copper was monitored with electron backscattering diffraction. An increase in void area was found to occur after cycling. This is thought to be the major contributing factor in the signal degradation of the TSVs, since no microstructural changes were observed in the copper

Local Epitaxial Overgrowth for Stacked Complementary MOS Transistor Pairs

A three-dimensional silicon processing technology for CMOS circuits was developed and characterized. The first fully depleted SOI devices with individually biasable gates on both sides of the silicon film were realized. A vertically stacked CMOS Inverter built by lateral overgrowth was reported for the first time. Nucleation-free epitaxial lateral overgrowth of silicon over thin oxides was developed for both a pancake and a barrel-type epitaxy reactor: This process was optimized to limit damage to gate oxides and minimize dopant diffusion within the Substrate. Autodoping from impurities of the MOS transistors built in the substrate was greatly reduced. A planarisation technique was developed to reduce the silicon film thickness from 13μm to below 0.5μm for full depletion. Chemo-mechanical polishing was modified to yield an automatic etch stop with the corresponding control and uniformity of the silicon film. The resulting wafer topography is more planar than in a conventional substrate CMOS process. PMOS transistors which match the current drive of bulk NM0S devices of equal geometry were characterized, despite the three-times lower hole mobility. Devices realized in the substrate, at the bottom and on top of the SOI film were essentially indistinguishable from bulk devices. A novel device with two insulated gates controlling the same channel was characterized. Inverters were realized both as joint-gate configuration and with symmetric performance of n- and p-channel. These circuits were realized in the area of a single NMOS transistor

A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

Evaluation of Silicon Selective Epitaxial Growth Defects using the Sidewall Gate Controlled Diode

Selective Epitaxial Growth (SEG) of silicon has shown great potential for advanced integrated circuit technologies. Before SEG can be fully utilized, sidewall defects must be reduced or at least controlled. The phenomena responsible for these defects were not understood, therefore more quantification of the sidewall defects is necessary. Walled diodes have been used to measure the sidewall leakage currents, but are susceptible to problems which make them poor devices for comparing different sidewall interfaces. A new device structure, the Sidewall Gate Controlled Diode (SGCD), is presented for the quantification of the defects near the SEG sidewall. The SGCD is shown to have advantages over the use of walled diodes despite the complex fabrication process required to build it. The development of the fabrication process for this device and the verification of its useful operation are presented. After the operation of the SGCD was verified, the device was used to evaluate the effects of various SEG deposition parameters on the sidewall defect density. This study determined that lower temperature, slower growth rate depositions followed with an in-situ hydrogen anneal generally reduced the defect density. Inconsistencies in the results also indicated that the profile of the sidewall may also influence the defect density at the SEG/oxide sidewall