Bulk-driven flipped voltage follower

A voltage buffer so-called the bulk-driven flipped voltage follower is presented. This proposal is based on the flipped voltage follower (FVF) technique, but a bulk-driven MOSFET with the replica-biased scheme is utilized for the input device to eliminate the DC level shift. The proposed buffer has been designed and simulated with a 0.35 mum CMOS technology. The input current and capacitance of our proposal are 1.5 pA and 9.3 fF respectively, and with 0.8 V peak-to-peak 500 kHz input, the total harmonic distortion is 0.5% for a 10 pF load. This circuit can operate from a single 1.2 V power supply and consumes only 2.5 muA

Design of a correlator for UWB transceivers

Master'sMASTER OF ENGINEERIN

Exploiting the bulk-driven approach in CMOS analogue amplifier design

This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused – at the input-stage of differential pairs, at the source followers, and at the cascode devices. For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the author’s best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented. The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of the OTA exceeds 60dB using a 0.35μm CMOS technology. The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results

Exploiting the bulk-driven approach in CMOS analogue amplifier design

This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused – at the input-stage of differential pairs, at the source followers, and at the cascode devices. For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the author’s best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented. The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of the OTA exceeds 60dB using a 0.35μm CMOS technology. The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results

Integrated Circuits for Medical Ultrasound Applications: Imaging and Beyond

Medical ultrasound has become a crucial part of modern society and continues to play a vital role in the diagnosis and treatment of illnesses. Over the past decades, the develop- ment of medical ultrasound has seen extraordinary progress as a result of the tremendous research advances in microelectronics, transducer technology and signal processing algorithms. How- ever, medical ultrasound still faces many challenges including power-efficient driving of transducers, low-noise recording of ultrasound echoes, effective beamforming in a non-linear, high- attenuation medium (human tissues) and reduced overall form factor. This paper provides a comprehensive review of the design of integrated circuits for medical ultrasound applications. The most important and ubiquitous modules in a medical ultrasound system are addressed, i) transducer driving circuit, ii) low- noise amplifier, iii) beamforming circuit and iv) analog-digital converter. Within each ultrasound module, some representative research highlights are described followed by a comparison of the state-of-the-art. This paper concludes with a discussion and recommendations for future research directions

Plasmonic color filter array, high performance analog to digital converter architectures and novel circuit techniques

Part I: Plasmonic color filters can be manufactured at lower cost since they can be fabricated in single lithographic process step as compared to Fabry-Perot based filters. In addition, they have narrow passband making resolving sharp features in sample spectrum possible. Due to these benefits, in this thesis, Plasmonic color filters are investigated as alternative to conventional color filters and their feasibility for spectroscopy demonstrated through reconstruction of 6 sample spectra by using a set of 20 color filters. The error in reconstructed sample spectra is less than 0.137 root mean squared error across all samples. Part II: A novel 12-bit pipelined successive approximation analog to digital converter is investigated for high speed data conversion. The design was implemented in TSMC 65nm process to demonstrate the feasibility of the architecture. Furthermore, a high dynamic range audio delta sigma modulator using pseudo-pseudo differential topology was investigated and feasibility simulated using TSMC 65nm process. In addition, various novel systems and circuit techniques including efficient calibration of feedback digital to analog converters, new boosted switch and push-pull source follower circuits were investigated to improve upon existing circuit topologies

Low-Noise Energy-Efficient Sensor Interface Circuits

Today, the Internet of Things (IoT) refers to a concept of connecting any devices on network where environmental data around us is collected by sensors and shared across platforms. The IoT devices often have small form factors and limited battery capacity; they call for low-power, low-noise sensor interface circuits to achieve high resolution and long battery life. This dissertation focuses on CMOS sensor interface circuit techniques for a MEMS capacitive pressure sensor, thermopile array, and capacitive microphone. Ambient pressure is measured in the form of capacitance. This work propose two capacitance-to-digital converters (CDC): a dual-slope CDC employs an energy efficient charge subtraction and dual comparator scheme; an incremental zoom-in CDC largely reduces oversampling ratio by using 9b zoom-in SAR, significantly improving conversion energy. An infrared gesture recognition system-on-chip is then proposed. A hand emits infrared radiation, and it forms an image on a thermopile array. The signal is amplified by a low-noise instrumentation chopper amplifier, filtered by a low-power 30Hz LPF to remove out-band noise including the chopper frequency and its harmonics, and digitized by an ADC. Finally, a motion history image based DSP analyzes the waveform to detect specific hand gestures. Lastly, a microphone preamplifier represents one key challenge in enabling voice interfaces, which are expected to play a dominant role in future IoT devices. A newly proposed switched-bias preamplifier uses switched-MOSFET to reduce 1/f noise inherently.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137061/1/chaseoh_1.pd

Analog Implementation of Fractional-Order Elements and Their Applications

With advancements in the theory of fractional calculus and also with widespread engineering application of fractional-order systems, analog implementation of fractional-order integrators and differentiators have received considerable attention. This is due to the fact that this powerful mathematical tool allows us to describe and model a real-world phenomenon more accurately than via classical “integer” methods. Moreover, their additional degree of freedom allows researchers to design accurate and more robust systems that would be impractical or impossible to implement with conventional capacitors. Throughout this thesis, a wide range of problems associated with analog circuit design of fractional-order systems are covered: passive component optimization of resistive-capacitive and resistive-inductive type fractional-order elements, realization of active fractional-order capacitors (FOCs), analog implementation of fractional-order integrators, robust fractional-order proportional-integral control design, investigation of different materials for FOC fabrication having ultra-wide frequency band, low phase error, possible low- and high-frequency realization of fractional-order oscillators in analog domain, mathematical and experimental study of solid-state FOCs in series-, parallel- and interconnected circuit networks. Consequently, the proposed approaches in this thesis are important considerations in beyond the future studies of fractional dynamic systems

Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces

Design of Discrete-time Chaos-Based Systems for Hardware Security Applications

Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices