Investigation Of The Fluid/Structure Interaction In Moulded Underfill Process

The rapid development of portable electronic devices, such as iPad, iPhone, iPod, and laptop, propels the integrated circuit (IC) packaging technology toward miniaturization characterized by high capacity and compactness of IC package. The scaling down of IC package size has given challenges to the engineers and IC designers in maintaining package reliability. In moulded underfill (MUF) process, the interaction between fluid (EMC) and structure (silicon chip and solder bump) yields unintended deformation and stress that may cause defects and reduce package reliability. Thus, the understanding of the FSI phenomenon is essential for the engineers and IC designers to tackle these problems. Therefore, the MUF process considering FSI aspect was the focus of this research. The FSI simulation was performed by finite volume based (FLUENT) and finite element based (ABAQUS) software through the MpCCI coupling technique for the simultaneous analysis. The capability of the software in handling encapsulation problems was examined by comparing the predicted results with previous scholars’ works and the current scaled-up MUF encapsulation processes. The scaled-up MUF encapsulation processes were fabricated in transparent for better visualization of FSI phenomenon, flow and void formation mechanisms. In the simulation, the Castro-Macosko viscosity model was written into UDFs to describe the EMC fluid behaviour. The accurateness of the UDFs has been proven excellent in modelling the rheological fluid behaviour during the encapsulation process

Investigation Of Wire Sweep During Pbga Encapsulation Process Using Fluid Structure Interaction

The reduction of IC chip size has a significant impact to the modern electronic industry especially on the circuit design and IC assembly process. The increasing of I/O counts in a small scale IC chip result in severe wire deformation and deformation issues during transfer moulding process. In this research, visualization of wire sweep phenomenon during the encapsulation process of plastic ball grid array (PBGA) package is studied through a three-dimensional (3D) fluid structure interaction (FSI) technique; which FV- and FE-based software are connected by using mesh-based parallel code coupling interface (MpCCI). The effect of polymer rheology, inlet pressure, arrangement of inlet gate, number of stacked die, wire diameter and size of mould cavity vents, on the melt flow behaviour, wire sweep, filling time, cavity pressure and stress distributions, are mainly studied. A 3D model of mould and wires was created by using GAMBIT, and the fluid/structure interaction was simulated by using FLUENT and ABAQUS software integrated with MpCCI for the real-time calculations. The Castro-Macosko model and Kamal model are used to incorporate the polymer rheology and the Volume of Fluid (VOF) technique is applied for melt front tracking. User-defined functions (UDFs) were incorporated to allow the curing kinetics. However, in the experimental work, the effects of FSI phenomenon in the PBGA package was studied using a scaled-up package size to mimic the encapsulation process. The effects of stacked die, inlet gate arrangement, outlet vent, and inlet pressure of mould cavity on the melt flow behaviour and wire sweep were xxxiii investigated. The constant viscosity of test fluid was utilised for experiment. The numerical results of melt front patterns and wire sweep were compared with the experimental results and it was found in good conformity. Three types of Epoxy Moulding Compound (EMC) were utilized for the study of fluid flow within the mould cavity. The melt front profiles and viscosity versus shear rate for all cases were analysed and presented. The numerical results of melt front behaviour and wire sweep were compared with the previous experimental results and found in good agreement. In the present study, the lower viscosity shows the lower air trap, lower pressure distributions and lower wire deformation. Optimised design of the PBGA gives better PBGA encapsulation process and minimises the wire sweep. The physical and process parameter (i.e., pressure inlet, wire diameter, vent height) were optimised via response surface methodology (RSM) using central composite design (CCD) to minimise the deformation of wire sweep, filling time and void in package during the PBGA encapsulation process. Fluid structure interaction (FSI) was considered in the optimisation of the PBGA encapsulation process. The optimum empirical models were tested and well confirmed with the simulation results. The optimum design of the PBGA with 12 wires for both physical and process parameters ware characterised by 5.57 MPa inlet pressure, 0.05 mm wire diameter, and 0.36 mm vent height. Therefore, the strength of MpCCI code coupling in handling FSI problems is proven to be excellent. This present work is expected to be a reference and guideline for microelectronics industry

Effects of Aspect Ratio in Moulded Packaging Considering Fluid/Structure Interaction: A CFD Modelling Approach

The fluid/structure interaction (FSI) investigations of stacked chip in encapsulation process of moulded underfill packaging using the two-way Coupling method with ANSYS Fluent and ANSYS Structural solvers are presented. The FSI study is executed with different aspect ratio of stacked chip on the mould filling during the encapsulation process. The simulation results in the FSI study is well validated with experimental setup. The epoxy moulding compound (EMC) and structure (chip) interaction is analyzed for better understanding the FSI phenomenon.Von Mises stresses experienced by the chip also be monitored for risk of chip cracking. The proposed analysis is anticipated to be a recommendation in the chip design and improvement of 3D integration packages

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast

Experimental and Numerical Thermal Analysis for Advanced Flip Chip Thermo-Compression Bonding via CMOS Microsensor Arrays and Finite Element Modelling

Thermo-compression bonding (TCB) relies on uniform thermal distribution during microelectronic packaging processes to ensure reliable interconnects are formed. During any TCB processes, the thermal application must uniformly distribute heat in order to produce robust, thoroughly bonded packages without being damaged due to thermo-mechanical effects. To better control and develop TCB processes, further insight through thermal analysis is required. Due to the form factors and complexity involved in TCB, it is difficult to accurately extract viable information such as temperature variation, lateral and vertical gradients, or interfacial bonding temperatures. To extract real time in-situ temperature and force signals, a microsensor array was used to observe any thermo-mechanical features recorded during emulated TCB processes. Algorithms were developed to post-process the signals and produce quantifiable data. Finite element models were developed to verify the experimental thermal responses and subsequently post-analyze the numerical results. Models formed through hybridized contact resistance layers as well as surface contact models are also discussed. Several features were identified and quantified: maximum heating rates, location of maximum lateral thermal gradients, internal joint thermal distributions, knee-region slope analysis and joint to joint thermal variation. The experimental responses in combination with numerical analyses show evidence that thermal applications during TCB is robust. Low thermal variation was found with respect to joint to joint temperatures. Chip design was found to heavily influence cooling on the periphery edges of the bump array. The sensor chip temperatures were to found to be about ≈ 6 °C lower than the extracted bump temperatures, signifying the use of microsensor arrays could be developed as accurate tools for thermal process control during TCB

Design and reliability of polymeric packages for high voltage power semiconductors

This thesis focuses on the development of a novel polymer based housing for power thyristor devices typically used in long distance high voltage direct current (HVDC) transmission. Power thyristor devices used in HVDC power conversion stations are typically packaged in a hermetically sealed ceramic housing and have demonstrated an excellent history of reliability and performance. However, to avoid increasing the number of thyristors in future higher powered HVDC schemes thyristors having higher power ratings at 8.5 kV and sizes at 125 mm and 150 mm diameters are sought for implementation to achieve higher transmission ratings of, for example, 4000 A at +/- 800 kV. The main disadvantages of such large ceramic-based packages are higher processing cost and weight whilst robustness is also a concern. To overcome these issues, replacing the current ceramic housing with a polymeric material has been investigated in this project. The advantages it is anticipated such packages will provide include lower cost, less weight, robustness, recyclability, etc. However, some challenges it will also offer are: non-hermeticity i.e. polymers are moisture and gas permeable, potentially more complex manufacturing routes, and different electrical, mechanical and thermal properties compared to ceramic materials. The work presented in this thesis was part of a larger project where these challenges have been addressed by developing and testing a prototype polymeric thyristor housing. The prototype is aimed at demonstrating that polymer packages can deliver performance and reliability comparable to, if not better than, current ceramic packages. In this thesis, it is the package development and reliability related studies that are discussed. Because the housings will experience severe electrical stresses and various thermal excursions during their service life, the electrical and thermo-mechanical behaviour of the polymer housing was studied using finite element analysis to gain an understanding of the effects of various design variables and materials properties on performance and the tradeoffs between performance and manufacturability. From these modelling studies, design guidelines have been established for the future development of polymer housings. On the other hand, to identify the physics-of-failure of the prototype that was manufactured as part of the project, accelerated life tests were performed to study its reliability. The knowledge gained from the polymer prototype development was then applied to the design of a larger 125 mm diameter housing using the Taguchi method of experimental design

Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips

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Fiabilité de l’underfill et estimation de la durée de vie d’assemblages microélectroniques

Abstract : In order to protect the interconnections in flip-chip packages, an underfill material layer is used to fill the volumes and provide mechanical support between the silicon chip and the substrate. Due to the chip corner geometry and the mismatch of coefficient of thermal expansion (CTE), the underfill suffers from a stress concentration at the chip corners when the temperature is lower than the curing temperature. This stress concentration leads to subsequent mechanical failures in flip-chip packages, such as chip-underfill interfacial delamination and underfill cracking. Local stresses and strains are the most important parameters for understanding the mechanism of underfill failures. As a result, the industry currently relies on the finite element method (FEM) to calculate the stress components, but the FEM may not be accurate enough compared to the actual stresses in underfill. FEM simulations require a careful consideration of important geometrical details and material properties. This thesis proposes a modeling approach that can accurately estimate the underfill delamination areas and crack trajectories, with the following three objectives. The first objective was to develop an experimental technique capable of measuring underfill deformations around the chip corner region. This technique combined confocal microscopy and the digital image correlation (DIC) method to enable tri-dimensional strain measurements at different temperatures, and was named the confocal-DIC technique. This techique was first validated by a theoretical analysis on thermal strains. In a test component similar to a flip-chip package, the strain distribution obtained by the FEM model was in good agreement with the results measured by the confocal-DIC technique, with relative errors less than 20% at chip corners. Then, the second objective was to measure the strain near a crack in underfills. Artificial cracks with lengths of 160 μm and 640 μm were fabricated from the chip corner along the 45° diagonal direction. The confocal-DIC-measured maximum hoop strains and first principal strains were located at the crack front area for both the 160 μm and 640 μm cracks. A crack model was developed using the extended finite element method (XFEM), and the strain distribution in the simulation had the same trend as the experimental results. The distribution of hoop strains were in good agreement with the measured values, when the model element size was smaller than 22 μm to capture the strong strain gradient near the crack tip. The third objective was to propose a modeling approach for underfill delamination and cracking with the effects of manufacturing variables. A deep thermal cycling test was performed on 13 test cells to obtain the reference chip-underfill delamination areas and crack profiles. An artificial neural network (ANN) was trained to relate the effects of manufacturing variables and the number of cycles to first delamination of each cell. The predicted numbers of cycles for all 6 cells in the test dataset were located in the intervals of experimental observations. The growth of delamination was carried out on FEM by evaluating the strain energy amplitude at the interface elements between the chip and underfill. For 5 out of 6 cells in validation, the delamination growth model was consistent with the experimental observations. The cracks in bulk underfill were modelled by XFEM without predefined paths. The directions of edge cracks were in good agreement with the experimental observations, with an error of less than 2.5°. This approach met the goal of the thesis of estimating the underfill initial delamination, areas of delamination and crack paths in actual industrial flip-chip assemblies.Afin de protéger les interconnexions dans les assemblages, une couche de matériau d’underfill est utilisée pour remplir le volume et fournir un support mécanique entre la puce de silicium et le substrat. En raison de la géométrie du coin de puce et de l’écart du coefficient de dilatation thermique (CTE), l’underfill souffre d’une concentration de contraintes dans les coins lorsque la température est inférieure à la température de cuisson. Cette concentration de contraintes conduit à des défaillances mécaniques dans les encapsulations de flip-chip, telles que la délamination interfaciale puce-underfill et la fissuration d’underfill. Les contraintes et déformations locales sont les paramètres les plus importants pour comprendre le mécanisme des ruptures de l’underfill. En conséquent, l’industrie utilise actuellement la méthode des éléments finis (EF) pour calculer les composantes de la contrainte, qui ne sont pas assez précises par rapport aux contraintes actuelles dans l’underfill. Ces simulations nécessitent un examen minutieux de détails géométriques importants et des propriétés des matériaux. Cette thèse vise à proposer une approche de modélisation permettant d’estimer avec précision les zones de délamination et les trajectoires des fissures dans l’underfill, avec les trois objectifs suivants. Le premier objectif est de mettre au point une technique expérimentale capable de mesurer la déformation de l’underfill dans la région du coin de puce. Cette technique, combine la microscopie confocale et la méthode de corrélation des images numériques (DIC) pour permettre des mesures tridimensionnelles des déformations à différentes températures, et a été nommée le technique confocale-DIC. Cette technique a d’abord été validée par une analyse théorique en déformation thermique. Dans un échantillon similaire à un flip-chip, la distribution de la déformation obtenues par le modèle EF était en bon accord avec les résultats de la technique confocal-DIC, avec des erreurs relatives inférieures à 20% au coin de puce. Ensuite, le second objectif est de mesurer la déformation autour d’une fissure dans l’underfill. Des fissures artificielles d’une longueuer de 160 μm et 640 μm ont été fabriquées dans l’underfill vers la direction diagonale de 45°. Les déformations circonférentielles maximales et principale maximale étaient situées aux pointes des fissures correspondantes. Un modèle de fissure a été développé en utilisant la méthode des éléments finis étendue (XFEM), et la distribution des contraintes dans la simuation a montré la même tendance que les résultats expérimentaux. La distribution des déformations circonférentielles maximales était en bon accord avec les valeurs mesurées lorsque la taille des éléments était plus petite que 22 μm, assez petit pour capturer le grand gradient de déformation près de la pointe de fissure. Le troisième objectif était d’apporter une approche de modélisation de la délamination et de la fissuration de l’underfill avec les effets des variables de fabrication. Un test de cyclage thermique a d’abord été effectué sur 13 cellules pour obtenir les zones délaminées entre la puce et l’underfill, et les profils de fissures dans l’underfill, comme référence. Un réseau neuronal artificiel (ANN) a été formé pour établir une liaison entre les effets des variables de fabrication et le nombre de cycles à la délamination pour chaque cellule. Les nombres de cycles prédits pour les 6 cellules de l’ensemble de test étaient situés dans les intervalles d’observations expérimentaux. La croissance de la délamination a été réalisée par l’EF en évaluant l’énergie de la déformation au niveau des éléments interfaciaux entre la puce et l’underfill. Pour 5 des 6 cellules de la validation, le modèle de croissance du délaminage était conforme aux observations expérimentales. Les fissures dans l’underfill ont été modélisées par XFEM sans chemins prédéfinis. Les directions des fissures de bord étaient en bon accord avec les observations expérimentales, avec une erreur inférieure à 2,5°. Cette approche a répondu à la problématique qui consiste à estimer l’initiation des délamination, les zones de délamination et les trajectoires de fissures dans l’underfill pour des flip-chips industriels

Non-destructive evaluation of solder joint reliability

A through life non-destructive evaluation technique is presented in which a key solder joint feature, nucleating at the bump to silicon interface and propagating across a laminar crack plane is captured and tracked using acoustic microscopy imaging (AMI). The feasibility of this concept was successfully demonstrated by employing the measurement technique in combination with Finite Element Analysis (FEA) to study the impact of component floor plan layout on the reliability of electronics systems subjected to thermal cycling. A comprehensive review of current and emerging packaging and interconnect technologies has shown increasingly a move from conventional 2D to 3D packaging. These present new challenges for reliability and Non Destructive Evaluation (NDE) due to solder joints being hidden beneath the packaging, and not ordinarily visible or accessible for inspection. Solutions are developed using non-destructive testing (NDT) techniques that have the potential to detect and locate defects in microelectronic devices. This thesis reports on X-ray and Acoustic Micro Imaging (AMI) which have complementary image discriminating features. Gap type defects are hard to find using X-ray alone due to low contrast and spot size resolution, whereas AMI having better axial resolution has allowed cracks and delamination at closely spaced interfaces to be investigated. The application of AMI to the study of through life solder joint behaviour has been achieved for the first time. Finite Element Analysis and AMI performance were compared to measure solder joint reliability for several realistic test cases. AMI images were taken at regular intervals to monitor through- life behaviour. Image processing techniques were used to extract a diameter measurement for a laminar crack plane, within a solder joint damage region occurring at the bump to silicon interface. FEA solder joint reliability simulations for flip-chip and micro-BGA (mBGA) packages placed on FR4 PCB's were compared to the AMI measurement performance, with a reasonable level of correlation observed. Both techniques clearly showed significant reliability degradation of the critical solder joints located furthest from the neutral axis of the package, typically residing at the package corners. The technique also confirmed that circuit board thickness can affect interconnect reliability, as can floor plan. Improved correlation to the real world environment was achieved when simulation models considered the entire floor plan layout and constraints imposed on the circuit board assembly. This thesis established a novel through life solder joint evaluation method crucial to the development of better physics of failure models and the advancement of model based prognostics in electronics systems