High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

異種ダイレット積層を用いたフレキシブルハイブリッドデバイスの集積技術に関する研究

Tohoku University福島誉史課

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Novel 3-D IC technology

textFor many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).Electrical and Computer Engineerin

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Commercialization of low temperature copper thermocompression bonding for 3D integrated circuits

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2008.Includes bibliographical references (p. 84-87).Wafer bonding is a key process and enabling technology for realization of three-dimensional integrated circuits (3DIC) with reduced interconnect delay and correspondingly increased circuit speed and decreased power dissipation, along with an improved form factor and portability. One of the most recent novel and promising wafer bonding approaches to realizing 3DIC is Low Temperature Thermocompression (LTTC) bonding using copper (Cu) as the bonding interface material. This thesis investigates the LTTC bonding approach in terms of its technological implications in contrast to other conventional bonding approaches. The various technological aspects pertaining to LTTC are comprehensively explored and analyzed. In addition to this, the commercialization potential for this technology is also studied and the economic viability of this process in production is critically evaluated using suitable cost models. Based on the technological and economic outlook, the potential for commercialization of LTTC is gauged.by Raghavan Nagarajan.M.Eng

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy