1,184 research outputs found
Design and implementation of an electro-optical backplane with pluggable in-plane connectors
The design, implementation and characterisation of an electro-optical
backplane and an active pluggable in-plane optical connector technology
is presented. The connection architecture adopted allows line cards to
be mated to and unmated from a passive electro-optical backplane with
embedded polymeric waveguides. The active connectors incorporate a
photonics interface operating at 850 nm and a mechanism to passively
align the interface to the optical waveguides embedded in the backplane.
A demonstration platform has been constructed to assess the viability of
embedded electro-optical backplane technology in dense data storage
systems. The demonstration platform includes four switch cards, which
connect both optically and electronically to the electro-optical backplane
in a chassis. These switch cards are controlled by a single board
computer across a Compact PCI bus on the backplane. The electrooptical
backplane is comprised of copper layers for power and low speed
bus communication and one polymeric optical layer, wherein waveguides
have been patterned by a direct laser writing scheme. The optical
waveguide design includes densely arrayed multimode waveguides with
a centre to centre pitch of 250ÎŒm between adjacent channels, multiple
cascaded waveguide bends, non-orthogonal crossovers and in-plane
connector interfaces. In addition, a novel passive alignment method
has been employed to simplify high precision assembly of the optical
receptacles on the backplane. The in-plane connector interface is based
on a two lens free space coupling solution, which reduces susceptibility
to contamination. Successful transfer of 10.3 Gb/s data along multiple
waveguides in the electro-optical backplane has been demonstrated and
characterised
Evolution of system embedded optical interconnect in sub-top of rack data center systems
This research was funded by the EU FP7 project âPhoxTrotâ, for which it has received funding from the European Union Seventh Framework Programme (FP7/2007â2013) under grant agreement No. 318240, the Horizon2020 Nephele project (Grant No. 645212), the Horizon2020 COSMICC project (Grant No. 688516).In this paper we review key technological milestones in system embedded optical interconnects in data centers that have been achieved between 2014 and 2020 on major European Union research and development projects. This includes the development of proprietary optically enabled data storage and switch systems and optically enabled data storage and compute subsystems. We report on four optically enabled data center system demonstrators: LightningValley, ThunderValley2, Pegasus and Aurora, which include advanced optical circuits based on polymer waveguides and fibers and proprietary electro-optical connectors. We also report on optically enabled subsystems including Ethernet-connected hard disk drives and microservers. Both are designed in the same pluggable carrier form factor and with embedded optical transceiver and connector interfaces, thus allowing, for the first time, both compute and storage nodes to be optically interchangeable and directly interconnectable over long distances. Finally, we present the Nexus platform, which allows different optically enabled data center test systems and subsystems to be interconnected and comparatively characterized within a data center test environment.Publisher PDFPeer reviewe
Optimization of multi-gigabit transceivers for high speed data communication links in HEP Experiments
The scheme of the data acquisition (DAQ) architecture in High Energy Physics
(HEP) experiments consist of data transport from the front-end electronics
(FEE) of the online detectors to the readout units (RU), which perform online
processing of the data, and then to the data storage for offline analysis. With
major upgrades of the Large Hadron Collider (LHC) experiments at CERN, the data
transmission rates in the DAQ systems are expected to reach a few TB/sec within
the next few years. These high rates are normally associated with the increase
in the high-frequency losses, which lead to distortion in the detected signal
and degradation of signal integrity. To address this, we have developed an
optimization technique of the multi-gigabit transceiver (MGT) and implemented
it on the state-of-the-art 20nm Arria-10 FPGA manufactured by Intel Inc. The
setup has been validated for three available high-speed data transmission
protocols, namely, GBT, TTC-PON and 10 Gbps Ethernet. The improvement in the
signal integrity is gauged by two metrics, the Bit Error Rate (BER) and the Eye
Diagram. It is observed that the technique improves the signal integrity and
reduces BER. The test results and the improvements in the metrics of signal
integrity for different link speeds are presented and discussed
Fiber optic control system integration
A total fiber optic, integrated propulsion/flight control system concept for advanced fighter aircraft is presented. Fiber optic technology pertaining to this system is identified and evaluated for application readiness. A fiber optic sensor vendor survey was completed, and the results are reported. The advantages of centralized/direct architecture are reviewed, and the concept of the protocol branch is explained. Preliminary protocol branch selections are made based on the F-18/F404 application. Concepts for new optical tools are described. Development plans for the optical technology and the described system are included
A 10-Gb/s two-dimensional eye-opening monitor in 0.13-ÎŒm standard CMOS
An eye-opening monitor (EOM) architecture that can capture a two-dimensional (2-D) map of the eye diagram of a high-speed data signal has been developed. Two single-quadrant phase rotators and one digital-to-analog converter (DAC) are used to generate rectangular masks with variable sizes and aspect ratios. Each mask is overlapped with the received eye diagram and the number of signal transitions inside the mask is recorded as error. The combination of rectangular masks with the same error creates error contours that overall provide a 2-D map of the eye. The authors have implemented a prototype circuit in 0.13-ÎŒm standard CMOS technology that operates up to 12.5 Gb/s at 1.2-V supply. The EOM maps the input eye to a 2-D error diagram with up to 68-dB mask error dynamic range. The left and right halves of the eyes are monitored separately to capture horizontally asymmetric eyes. The chip consumes 330 mW and operates reliably with supply voltages as low as 1 V at 10 Gb/s. The authors also present a detailed analysis that verifies if the measurements are in good agreement with the expected results
The Level-0 Muon Trigger for the LHCb Experiment
A very compact architecture has been developed for the first level Muon
Trigger of the LHCb experiment that processes 40 millions of proton-proton
collisions per second. For each collision, it receives 3.2 kBytes of data and
it finds straight tracks within a 1.2 microseconds latency. The trigger
implementation is massively parallel, pipelined and fully synchronous with the
LHC clock. It relies on 248 high density Field Programable Gate arrays and on
the massive use of multigigabit serial link transceivers embedded inside FPGAs.Comment: 33 pages, 16 figures, submitted to NIM
GSFC Annual Scan Technology Review SpaceCube On-Board Processor Update
No abstract availabl
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