DEVELOPMENT OF NANO/MICROELECTROMECHANICAL SYSTEM (N/MEMS) SWITCHES

Ph.DDOCTOR OF PHILOSOPH

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures &gt;225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 μm , on-resistance of 200 kΩ , and a via pitch of 0.4 μm , all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to 15× improvement in energy efficiency.QC 20180412</p

CMOS Compatible Thin-Film ALD Tungsten Nanoelectromechanical Devices

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3-5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5-3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-_lm NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 103. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin- _lm NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered

DEVELOPMENT OF NEMS RELAYS IN LOGIC COMPUTATION AND RUGGED ELECTRONICS

Ph.DDOCTOR OF PHILOSOPH

Carbon nano-relays for low power switching

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 147-153).In this thesis two unique carbon based nanoelectromechanical switches or carbon nano-relays are demonstrated as a toolkit for investigating NEMs based low power switching. The first is a vertical carbon nano-relay, consisting of a vertically aligned carbon nanotube/fiber (CN) between two contacts and operated by pull-off, and the second, a double graphene switch, consisting of two electromechanically actuated stacked layers of polycrystalline graphene. Vertical carbon nano-relays were initially prototyped by inserting a CN between two contacts through the use of a nanopositioner. The prototype demonstrated pull-off operation and multiple switching. To our knowledge this is the only example to date of a multiple-use NEMs switch that operates with pull-off. Next a wafer integrated device was fabricated. Although pull-in was demonstrated in these integrated devices, pull-off was not possible primarily due to limitations in CN growth, which were also investigated. In the work on a double graphene switch we demonstrated an electromechanical switch comprising two polycrystalline graphene films, each deposited using ambient pressure chemical vapor deposition (CVD). The top film is pulled into electrical contact with the bottom film by application of approximately 5V between the layers. Contact is broken by mechanical restoring forces after bias is removed. The device switches several times before tearing. Demonstration of multiple switching at low voltage confirms that graphene is an attractive material for electromechanical switches.by Kaveh Mehdi Milaninia.Ph.D

Non-invasive power gating techniques for bursty computation workloads using micro-electro-mechanical relays

PhD ThesisElectrostatically-actuated Micro-Electro-Mechanical/Nano-Electro- Mechanical (MEM/NEM) relays are promising devices overcoming the energy-efficiency limitations of CMOS transistors. Many exploratory research projects are currently under way investigating the mechanical, electrical and logical characteristics of MEM/NEM relays. One particular issue that this work addresses is the need for a scalable and accurate physical model of the MEM/NEM switches that can be plugged into the standard EDA software. The existing models are accurate and detailed but they suffer from the convergence problem. This problem requires finding ad-hoc workarounds and significantly impacts the designer’s productivity. In this thesis we propose a new simplified Verilog-AMS model. To test scalability of the proposed model we cross-checked it against our analysis of a range of benchmark circuits. Results show that, compared to standard models, the proposed model is sufficiently accurate with an average of 6% error and can handle larger designs without divergence. This thesis also investigates the modelling, designing and optimization of various MEM/NEM switches using 3D Finite Element Analysis (FEA) performed by the COMSOL multiphysics simulation tool. An extensive parametric sweep simulation is performed to study the energy-latency trade-offs of MEM/NEM relays. To accurately simulate MEMS/NEMS-based digital circuits, a Verilog-AMS model is proposed based on the evaluated parameters obtained from the multiphysics simulation tool. This allows an accurate calibration of the MEM/NEM relays with a significant reduction in simulation speed compared to that of 3D FEA exercised on COMSOL tool. The effectiveness of two power gating approaches in asynchronous micropipelines is also investigated using MEM/NEM switches and sleep transistors in reducing idle power dissipation with a particular target throughput. Sleep transistors are traditionally used to power gate idle circuits, however, these transistors have fundamental limitations in their effectiveness. Alternatively, MEM/NEM relays with zero leakage current can achieve greater energy savings under a certain data rate and design architecture. An asynchronous FIR filter 4 phase bundled data handshake protocol is presented. Implementation is accomplished in 90nm technology node and simulation exercised at various data rates and design complexities. It was demonstrated that our proposed approach offers 69% energy improvements at a data rate 1KHz compared to 39% of the previous work. The current trends for greater heterogeneity in future Systems-on- Chip (SoC) do not only concern their functionality but also their timing and power aspects. The increasing diversity of timing and power supply conditions, and associated concurrently operating modes, within an SoC calls for more efficient power delivery networks (PDN) for battery operated devices. This is especially important for systems with mixed duty cycling, where some parts are required to work regularly with low-throughput while other parts are activated spontaneously, i.e. in bursts. To improve their reaction time vs energy efficiency, this work proposes to incorporate a power-switching network based on MEM relays to switch the SoC power-performance state (PPS) into an active mode while eliminating the leakage current when it is idle. Results show that even with today0s large and high pull-in voltages, a MEM-relay-based power switching network (PSN) can achieve a 1000x savings in energy compared to its CMOS counterpart for low duty cycle. A simple case of optimising an on-chip charge pump required to switch-on the relay has been investigated and its energy-latency overhead has been evaluated. Heterogeneous many-core systems are increasingly being employed in modern embedded platforms for high throughput at low energy cost considerations. These applications typically exhibit bursty workloads that provide opportunities to minimize system energy. CMOS-based power gating circuitry, typically consisting of sleep transistors, is used as an effective technique for idle energy reduction in such applications. However, these transistors contribute high leakage current when driving large capacitive loads, making effective energy minimization challenging. This thesis proposes a novel MEMS-based idle energy control approach. Core to this approach is an integrated sleep mode management based on the performance-energy states and bursty workloads indicated by the performance counters. A number of PARSEC benchmark applications are used as case studies of bursty workloads, including CPU- and memory- intensive ones. These applications are exercised on an Exynos 5422 heterogeneous many-core platform, engineered with a performance counter facilities, showing 55.5% energy savings compared with an on-demand governor. Furthermore, an extensive trade-off analysis demonstrates the comparative advantages of the MEMS-based controller, including zero-leakage current and non-invasive implementations suitable for commercial off-the-shelf systems.Higher committee of education development in Iraq (HCED

Microelectromechanical Systems and Devices

The advances of microelectromechanical systems (MEMS) and devices have been instrumental in the demonstration of new devices and applications, and even in the creation of new fields of research and development: bioMEMS, actuators, microfluidic devices, RF and optical MEMS. Experience indicates a need for MEMS book covering these materials as well as the most important process steps in bulk micro-machining and modeling. We are very pleased to present this book that contains 18 chapters, written by the experts in the field of MEMS. These chapters are groups into four broad sections of BioMEMS Devices, MEMS characterization and micromachining, RF and Optical MEMS, and MEMS based Actuators. The book starts with the emerging field of bioMEMS, including MEMS coil for retinal prostheses, DNA extraction by micro/bio-fluidics devices and acoustic biosensors. MEMS characterization, micromachining, macromodels, RF and Optical MEMS switches are discussed in next sections. The book concludes with the emphasis on MEMS based actuators

Gestión de jerarquías de memoria híbridas a nivel de sistema

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadoras y Automática y de Ku Leuven, Arenberg Doctoral School, Faculty of Engineering Science, leída el 11/05/2017.In electronics and computer science, the term ‘memory’ generally refers to devices that are used to store information that we use in various appliances ranging from our PCs to all hand-held devices, smart appliances etc. Primary/main memory is used for storage systems that function at a high speed (i.e. RAM). The primary memory is often associated with addressable semiconductor memory, i.e. integrated circuits consisting of silicon-based transistors, used for example as primary memory but also other purposes in computers and other digital electronic devices. The secondary/auxiliary memory, in comparison provides program and data storage that is slower to access but offers larger capacity. Examples include external hard drives, portable flash drives, CDs, and DVDs. These devices and media must be either plugged in or inserted into a computer in order to be accessed by the system. Since secondary storage technology is not always connected to the computer, it is commonly used for backing up data. The term storage is often used to describe secondary memory. Secondary memory stores a large amount of data at lesser cost per byte than primary memory; this makes secondary storage about two orders of magnitude less expensive than primary storage. There are two main types of semiconductor memory: volatile and nonvolatile. Examples of non-volatile memory are ‘Flash’ memory (sometimes used as secondary, sometimes primary computer memory) and ROM/PROM/EPROM/EEPROM memory (used for firmware such as boot programs). Examples of volatile memory are primary memory (typically dynamic RAM, DRAM), and fast CPU cache memory (typically static RAM, SRAM, which is fast but energy-consuming and offer lower memory capacity per are a unit than DRAM). Non-volatile memory technologies in Si-based electronics date back to the 1990s. Flash memory is widely used in consumer electronic products such as cellphones and music players and NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. The rapid increase of leakage currents in Silicon CMOS transistors with scaling poses a big challenge for the integration of SRAM memories. There is also the case of susceptibility to read/write failure with low power schemes. As a result of this, over the past decade, there has been an extensive pooling of time, resources and effort towards developing emerging memory technologies like Resistive RAM (ReRAM/RRAM), STT-MRAM, Domain Wall Memory and Phase Change Memory(PRAM). Emerging non-volatile memory technologies promise new memories to store more data at less cost than the expensive-to build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. These new memory technologies combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the non-volatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. The research and information on these Non-Volatile Memory (NVM) technologies has matured over the last decade. These NVMs are now being explored thoroughly nowadays as viable replacements for conventional SRAM based memories even for the higher levels of the memory hierarchy. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional(3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years...En el campo de la informática, el término ‘memoria’ se refiere generalmente a dispositivos que son usados para almacenar información que posteriormente será usada en diversos dispositivos, desde computadoras personales (PC), móviles, dispositivos inteligentes, etc. La memoria principal del sistema se utiliza para almacenar los datos e instrucciones de los procesos que se encuentre en ejecución, por lo que se requiere que funcionen a alta velocidad (por ejemplo, DRAM). La memoria principal está implementada habitualmente mediante memorias semiconductoras direccionables, siendo DRAM y SRAM los principales exponentes. Por otro lado, la memoria auxiliar o secundaria proporciona almacenaje(para ficheros, por ejemplo); es más lenta pero ofrece una mayor capacidad. Ejemplos típicos de memoria secundaria son discos duros, memorias flash portables, CDs y DVDs. Debido a que estos dispositivos no necesitan estar conectados a la computadora de forma permanente, son muy utilizados para almacenar copias de seguridad. La memoria secundaria almacena una gran cantidad de datos aun coste menor por bit que la memoria principal, siendo habitualmente dos órdenes de magnitud más barata que la memoria primaria. Existen dos tipos de memorias de tipo semiconductor: volátiles y no volátiles. Ejemplos de memorias no volátiles son las memorias Flash (algunas veces usadas como memoria secundaria y otras veces como memoria principal) y memorias ROM/PROM/EPROM/EEPROM (usadas para firmware como programas de arranque). Ejemplos de memoria volátil son las memorias DRAM (RAM dinámica), actualmente la opción predominante a la hora de implementar la memoria principal, y las memorias SRAM (RAM estática) más rápida y costosa, utilizada para los diferentes niveles de cache. Las tecnologías de memorias no volátiles basadas en electrónica de silicio se remontan a la década de1990. Una variante de memoria de almacenaje por carga denominada como memoria Flash es mundialmente usada en productos electrónicos de consumo como telefonía móvil y reproductores de música mientras NAND Flash solid state disks(SSDs) están progresivamente desplazando a los dispositivos de disco duro como principal unidad de almacenamiento en computadoras portátiles, de escritorio e incluso en centros de datos. En la actualidad, hay varios factores que amenazan la actual predominancia de memorias semiconductoras basadas en cargas (capacitivas). Por un lado, se está alcanzando el límite de integración de las memorias Flash, lo que compromete su escalado en el medio plazo. Por otra parte, el fuerte incremento de las corrientes de fuga de los transistores de silicio CMOS actuales, supone un enorme desafío para la integración de memorias SRAM. Asimismo, estas memorias son cada vez más susceptibles a fallos de lectura/escritura en diseños de bajo consumo. Como resultado de estos problemas, que se agravan con cada nueva generación tecnológica, en los últimos años se han intensificado los esfuerzos para desarrollar nuevas tecnologías que reemplacen o al menos complementen a las actuales. Los transistores de efecto campo eléctrico ferroso (FeFET en sus siglas en inglés) se consideran una de las alternativas más prometedores para sustituir tanto a Flash (por su mayor densidad) como a DRAM (por su mayor velocidad), pero aún está en una fase muy inicial de su desarrollo. Hay otras tecnologías algo más maduras, en el ámbito de las memorias RAM resistivas, entre las que cabe destacar ReRAM (o RRAM), STT-RAM, Domain Wall Memory y Phase Change Memory (PRAM)...Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu

Electromechanical Lifting Actuation of a MEMS Cantilever and Nano-Scale Analysis of Diffusion in Semiconductor Device Dielectrics

This dissertation presents experimental and theoretical studies of physical phenomena in micro- and nano-electronic devices. Firstly, a novel and unproven means of electromechanical actuation in a micro-electro-mechanical system (MEMS) cantilever was investigated. In nearly all MEMS devices, electric forces cause suspended components to move toward the substrate. I demonstrated a design with the unusual and potentially very useful property of having a suspended MEMS cantilever lift away from the substrate. The effect was observed by optical micro-videography, by electrical sensing, and it was quantified by optical interferometry. The results agree with predictions of analytic and numerical calculations. One potential application is infrared sensing in which absorbed radiation changes the temperature of the cantilever, changing the duty cycle of an electrically-driven, repetitively closing micro-relay. Secondly, ultra-thin high-k gate dielectric layers in two 22 nm technology node semiconductor devices were studied. The purpose of the investigation was to characterize the morphology and composition of these layers as a means to verify whether the transmission electron microscope (TEM) with energy dispersive spectroscopy (EDS) could sufficiently resolve the atomic diffusion at such small length scales. Results of analytic and Monte-Carlo numerical calculations were compared to empirical data to validate the ongoing viability of TEM EDS as a tool for nanoscale characterization of semiconductor devices in an era where transistor dimensions will soon be less than 10 nm

Electromechanical Switches Fabricated by Electrophoretic Deposition of Single Wall Carbon Nanotube Films

University of Minnesota Ph.D. dissertation.August 2015. Major: Electrical/Computer Engineering. Advisor: Stephen Campbell. 1 computer file (PDF); xi, 110 pages.Power dissipation is a critical problem of CMOS devices especially for mobile applications. Many efforts have been made to solve the problem, but there are still major issues associated with scaling the device size. Micro electromechanical (MEMS) and nano electromechanical (NEMS) devices are one candidate to solve the problems because of their excellent standby leakage. However, the switches have a tradeoff between low operating power and high device speed. Suspended beams with low mass density and good mechanical properties provide a way to optimize the device. Carbon nanotubes (CNTs) have the low mass density and excellent mechanical properties to enable high performance MEMS/NEMS devices. However, the high temperature required for the direct synthesis for CNTs makes it difficult for them to be compatible with a substrate containing transistors. Therefore, continuous film deposition techniques are investigated with low temperature (< 300 C). Electrophoretic deposition (EPD) is a simple and versatile processing method to deposit carbon nanotubes on the substrate at room temperature. The movement of the charged CNTs in suspension occurs by an applied electric field. The deposited CNT film thickness can be controlled through the applied voltage and process time. We demonstrate the use of an EPD process to deposit various thicknesses of CNT films. Film thicknesses are studied as a function of, deposition time, electric field strength, and suspension concentration. The deposition mechanism of the EPD process for carbon nanotube layers was explained with experimental data. We determined the film mass density and electrical/optical properties of SWCNT films. Rutherford backscattering spectroscopy was used to determine the film mass density. Films created in this manner had a mass density that varies with thickness from 0.12 to 0.54 g/cm3 and a resistivity of 2.1410-3 Ω∙cm. For the mechanical property measurements, we describe a technique to fabricate free-standing thin films using modified Langmuir-Blodgett method. Then we extracted the Young’s modulus of the film from the load-displacement data from nanoindentation using the appropriate modeling. The Young’s modulus had a range of 4.72 to 5.67 GPa, independent of deposited thickness. We fabricated two-terminal fixed beam switches with SWCNT thin films using the EPD process. Device pull-in voltages under 1V were achieved by decreasing the air-gap. The pull-in voltages were compared with the calculated results using the device geometry and extracted Young’s modulus from nanoindentation. Generally good agreement was observed. Also, we found a range of 2.4 to 3.5 MHz resonant frequency. However, we encountered several problems with the device including a gradual turn-on, hysteresis between pull-in and pull-out voltage, changes in the pull-in voltages with repeated on-off cycling, and early failure due to moisture absorption during testing in the air. Mechanisms for these observations are postulated. Further work is needed to improve device performance and reliability