Design of a fault tolerant airborne digital computer. Volume 2: Computational requirements and technology

This final report summarizes the work on the design of a fault tolerant digital computer for aircraft. Volume 2 is composed of two parts. Part 1 is concerned with the computational requirements associated with an advanced commercial aircraft. Part 2 reviews the technology that will be available for the implementation of the computer in the 1975-1985 period. With regard to the computation task 26 computations have been categorized according to computational load, memory requirements, criticality, permitted down-time, and the need to save data in order to effect a roll-back. The technology part stresses the impact of large scale integration (LSI) on the realization of logic and memory. Also considered was module interconnection possibilities so as to minimize fault propagation

EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS

The growing applications for IoT devices have caused an increase in the study of low power consuming circuit design to meet the requirement of devices to operate for various months without external power supply. Scaling down the conventional CMOS causes various complications to design due to CMOS properties, therefore various non-conventional CMOS design techniques are being proposed that overcome the limitations. This thesis focuses on some of those emerging and novel low power design technique namely Adiabatic logic and low power devices like Magnetic Tunnel Junction (MTJ) and Carbon Nanotube Field Effect transistor (CNFET). Circuits that are used for large computations (multipliers, encryption engines) that amount to maximum part of power consumption in a whole chip are designed using these novel low power techniques

High Speed Low Area DA Based FIR Filter Using EGDI Adder

In this paper, we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter.  Generally, multipliers, adders, and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this multiplier less architecture is needed in the FIR filter. So Distributed Arithmetic architecture plays a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of the FIR filter and at the same time, the area will be decreased. The proposed design is synthesized and implemented in the Synapsis design compiler tool. The area, power delay product, frequency, area delay product, and power of the proposed design are calculated.  When we observe the proposed design has a 15% high-frequency rate when compared with the existing design. Also, the proposed design is more useful in signal, processing applications

High Speed Low Area DA Based FIR Filter Using EGDI Adder

In this paper, we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter.  Generally, multipliers, adders, and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this multiplier less architecture is needed in the FIR filter. So Distributed Arithmetic architecture plays a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of the FIR filter and at the same time, the area will be decreased. The proposed design is synthesized and implemented in the Synapsis design compiler tool. The area, power delay product, frequency, area delay product, and power of the proposed design are calculated.  When we observe the proposed design has a 15% high-frequency rate when compared with the existing design. Also, the proposed design is more useful in signal, processing applications

High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one

NASA Space Engineering Research Center for VLSI System Design

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems

Ultra high-density hybrid pixel sensors for the detection of charge particles

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