FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

128 mA CMOS LDO with 108 db PSRR at 2.4 MHz frequency

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency

Design of Analog CMOS Circuits for Batteryless Implantable Telemetry Systems

A wireless biomedical telemetry system is a device that collects biomedical signal measurements and transmits data through wireless RF communication. Testing medical treatments often involves experimentation on small laboratory animals, such as genetically modified mice and rats. Using batteries as a power source results in many practical issues, such as increased size of the implant and limited operating lifetime. Wireless power harvesting for implantable biomedical devices removes the need for batteries integrated into the implant. This will reduce device size and remove the need for surgical replacement due to battery depletion. Resonant inductive coupling achieves wireless power transfer in a manner modelled by a step down transformer. With this methodology, power harvesting for an implantable device is realized with the use of a large primary coil external to the subject, and a smaller secondary coil integrated into the implant. The signal received from the secondary coil must be regulated to provide a stable direct current (DC) power supply, which will be used to power the electronics in the implantable device. The focus of this work is on development of an electronic front-end for wireless powering of an implantable biomedical device. The energy harvesting front-end circuit is comprised of a rectifier, LDO regulator, and a temperature insensitive voltage reference. Physical design of the front-end circuit is developed in 0.13um CMOS technology with careful attention to analog layout issues. Post-layout simulation results are presented for each sub-block as well as the full front-end structure. The LDO regulator operates with supply voltages in the range of 1V to 1.5V with quiescent current of 10.5uA The complete power receiver front-end has a power conversion efficiency of up to 29%

A Silicon Germanium CMOS Linear Voltage Regulator for Wireless Agricultural Applications

This thesis presents the design, simulation and test results of a silicon germanium (SiGe) complementary metal-oxide-semiconductor (CMOS) linear regulator. The objective of the circuit is to power other analog devices regardless of the load current and input voltage changes. The application of this regulator is to be part of a project developing a miniaturized semiconductor platform that can be inserted into stems of crops in order to measure data inside the plant and then send it wirelessly to the user. The linear regulator was designed on a BiCMOS SiGe 0.13µm which is a GlobalFoundries process. It has been tested at room temperature and at 85 ºC with a supply voltage of 2.5 V and it holds an output of 1.2 V. The device demonstrates line regulation of 5 % and load regulation of 0.19 % as well as rejection of the power supply satisfying the specifications proposed

Design consideration in low dropout voltage regulator for batteryless power management unit

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology

An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma

STUDY OF FULLY-INTEGRATED LOW-DROPOUT REGULATORS

Department of Electrical EngineeringThis thesis focuses on the introduction of fully-integrated low-dropout regulators (LDOs). Recently, for the mobile and internet-of-things applications, the level of integration is getting higher. LDOs get popular in integrated circuit design including functions such as reducing switching ripples from high-efficiency regulators, cancelling spurs from other loads, and giving different supply voltages to loads. In accordance with load applications, choosing proper LDOs is important. LDOs can be classified by the types of power MOSEFT, the topologies of error amplifier, and the locations of dominant pole. Analog loads such as voltage-controlled oscillators and analog-to-digital converters need LDOs that have high power-supply-rejection-ratio (PSRR), high accuracy, and low noise. Digital loads such as DRAM and CPU need fast transient response, a wide range of load current providable LDOs. As an example, we present the design procedure of a fully-integrated LDO that obtains the desired PSRR. In analog LDOs, we discuss advanced techniques such as local positive feedback loop and zero path that can improve stability and PSRR performance. In digital LDOs, the techniques to improve transient response are introduced. In analog-digital hybrid LDOs, to achieve both fast transient and high PSRR performance in a fully-integrated chip, how to optimally combine analog and digital LDOs is considered based on the characteristics of each LDO type. The future work is extracted from the considerations and limitations of conventional techniques.clos