72 research outputs found
Intrinsic distortion of a fully differential BD-modulated Class-D amplifier with analog feedback
This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifier with analog feedback, i.e., one having a bridge-tied-load output configuration with negative feedback and ternary PWM signal. Notwithstanding the highly nonlinear nature of
the amplifier's operation, an extremely accurate closed-form expression for the audible output signal is derived and verified based on computer simulations. This expression demonstrates that there exist larger
high-order intrinsic distortions (e.g., 5th-order harmonic distortion and intermodulation distortion) for BD-modulation, compared to that for AD-modulation (binary PWM signal). Furthermore, the 3rd-order harmonic
distortion has a roughly parabolic response as a function of the magnitude of the input signal and reaches its peak when the modulation index of the input signal is around 0.7. Overall, the BD-modulated Class-D amplifier has a larger intrinsic distortion for small input signal but a smaller intrinsic distortion for large input signal,
compared to AD-modulated designs
Class D Audio Amplifier
This project consisted of the design, construction, and comparison testing of two implementations of analog pulse-width modulation Class D audio amplifiers. The main goal of the project was to maximize the efficiency of the amplifier designs while maintaining a high-power, low-noise output signal. PCB testing confirmed that the amplifiers met our goals of greater than 90% efficiency, less than 1% total harmonic distortion and greater than 50 W output power
Low Power High Efficiency Integrated Class-D Amplifier Circuits for Mobile Devices
The consumer’s demand for state-of-the-art multimedia devices such as smart phones and tablet computers has forced manufacturers to provide more system features to compete for a larger portion of the market share. The added features increase the power consumption and heat dissipation of integrated circuits, depleting the battery charge faster. Therefore, low-power high-efficiency circuits, such as the class-D audio amplifier, are needed to reduce heat dissipation and extend battery life in mobile devices. This dissertation focuses on new design techniques to create high performance class-D audio amplifiers that have low power consumption and occupy less space.
The first part of this dissertation introduces the research motivation and fundamentals of audio amplification. The loudspeaker’s operation and main audio performance metrics are examined to explain the limitations in the amplification process. Moreover, the operating principle and design procedure of the main class-D amplifier architectures are reviewed to provide the performance tradeoffs involved.
The second part of this dissertation presents two new circuit designs to improve the audio performance, power consumption, and efficiency of standard class-D audio amplifiers. The first work proposes a feed-forward power-supply noise cancellation technique for single-ended class-D amplifier architectures to improve the power-supply rejection ratio across the entire audio frequency range. The design methodology, implementation, and tradeoffs of the proposed technique are clearly delineated to demonstrate its simplicity and effectiveness. The second work introduces a new class-D output stage design for piezoelectric speakers. The proposed design uses stacked-cascode thick-oxide CMOS transistors at the output stage that makes possible to handle high voltages in a low voltage standard CMOS technology. The design tradeoffs in efficiency, linearity, and electromagnetic interference are discussed.
Finally, the open problems in audio amplification for mobile devices are discussed to delineate the possible future work to improve the performance of class-D amplifiers. For all the presented works, proof-of-concept prototypes are fabricated, and the measured results are used to verify the correct operation of the proposed solutions
Design of a Continuous-Time (CT) Sigma-Delta modulator for class D audio power amplifiers
Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadore
Realization of Integrable Low- Voltage Companding Filters for Portable System Applications
Undoubtedly, today’s integrated electronic systems owe their remarkable performance
primarily to the rapid advancements of digital technology since 1970s. The various
important advantages of digital circuits are: its abstraction from the physical details of
the actual circuit implementation, its comparative insensitiveness to variations in the
manufacturing process, and the operating conditions besides allowing functional
complexity that would not be possible using analog technology. As a result, digital
circuits usually offer a more robust behaviour than their analog counterparts, though
often with area, power and speed drawbacks. Due to these and other benefits, analog
functionality has increasingly been replaced by digital implementations.
In spite of the advantages discussed above, analog components are far from
obsolete and continue to be key components of modern electronic systems. There is
a definite trend toward persistent and ubiquitous use of analog electronic circuits in
day-to-day life. Portable electronic gadgets, wireless communications and the
widespread application of RF tags are just a few examples of contemporary
developments. While all of these electronic systems are based on digital circuitry,
they heavily rely on analog components as interfaces to the real world. In fact, many
modern designs combine powerful digital systems and complementary analog
components on a single chip for cost and reliability reasons. Unfortunately, the design
of such systems-on-chip (SOC) suffers from the vastly different design styles of
analog and digital components. While mature synthesis tools are readily available for
digital designs, there is hardly any such support for analog designers apart from wellestablished
PSPICE-like circuit simulators. Consequently, though the analog part
usually occupies only a small fraction of the entire die area of an SOC, but its design
often constitutes a major bottleneck within the entire development process.
Integrated continuous-time active filters are the class of continuous-time or
analog circuits which are used in various applications like channel selection in radios,
anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a
filter is the dynamic range; this is the ratio of the largest to the smallest signal that can
be applied at the input of the filter while maintaining certain specified performance.
The dynamic range required in the filter varies with the application and is decided by
the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the
capacitor area of an integrated active filter increases in proportion to its dynamic
range. This situation is incompatible with the needs of integrated systems, especially
battery operated ones. In addition to this fundamental dependence of power dissipation
on dynamic range, the design of integrated active filters is further complicated by the
reduction of supply voltage of integrated circuits imposed by the scaling down of
technologies to attain twin objective of higher speed and lower power consumption in
digital circuits. The reduction in power consumption with decreasing supply voltage
does not apply to analog circuits. In fact, considerable innovation is required with a
reduced supply voltage even to avoid increasing power consumption for a given signal
to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer.
A technique which has attracted the attention of circuit designers as a possible
route to filters with higher dynamic range per unit power consumption is
“companding”. Companding (compression-expansion) filters are a very promising
subclass of continuous-time analog filters, where the input (linear) signal is initially
compressed before it will be handled by the core (non-linear) system. In order to
preserve the linear operation of the whole system, the non-linear signal produced by
the core system is converted back to a linear output signal by employing an
appropriate output stage. The required compression and expansion operations are
performed by employing bipolar transistors in active region or MOS transistors in
weak inversion; the systems thus derived are known as logarithmic-domain (logdomain)
systems. In case MOS transistors operated in saturation region are employed,
the derived structures are known as Square-root domain systems. Finally, the third
class of companding filters can also be obtained by employing bipolar transistors in
active region or MOS transistors in weak inversion; the derived systems are known as
Sinh-domain systems. During the last several years, a significant research effort has been already
carried out in the area of companding circuits. This is due to the fact that their main
advantages are the capability for operation in low-voltage environment and large
dynamic range originated from their companding nature, electronic tunability of the
frequency characteristics, absence of resistors and the potential for operations in varied
frequency regions.Thus, it is obvious that companding filters can be employed for implementing
high-performance analog signal processing in diverse frequency ranges. For example,
companding filters could be used for realizing subsystems in: xDSL modems, disk
drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked
loops, FM stereo demodulator, touch-tone telephone tone decoder and
crossover network used in a three-way high-fidelity loudspeaker etc.
A number of design methods for companding filters and their building blocks
have been introduced in the literature. Most of the proposed filter structures operate
either above 1.5V or under symmetrical (1.5V) power supplies. According to data that
provides information about the near future of semiconductor technology, International
Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital
circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of
analog integrated circuits is the usage of low-voltage building blocks that use a single
0.5-1.5V power supply.
Therefore, the present investigation was primarily concerned with the study and
design of low voltage and low power Companding filters. The work includes the
study about: the building blocks required in implementing low voltage and low power
Companding filters; the techniques used to realize low voltage and low power
Companding filters and their various areas of application.
Various novel low voltage and low power Companding filter designs have been
developed and studied for their characteristics to be applied in a particular portable
area of application. The developed designs include the N-th order universal
Companding filter designs, which have been reported first time in the open literature.
Further, an endeavor has been made to design Companding filters with orthogonal
tuning of performance parameters so that the designs can be simultaneously used for
various features. The salient features of each of the developed circuit are described.
Electronic tunability is one of the major features of all of the designs. Use of
grounded capacitors and resistorless designs in all the cases makes the designs suitable
for IC technology. All the designs operate in a low-voltage and low-power
environment essential for portable system applications.
Unless specified otherwise, all the investigations on these designs are based on the
PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The
performance of each circuit has been validated by comparing the characteristics
obtained using simulation with the results present in the open literature.
The proposed designs could not be realized in silicon due to non-availability of
foundry facility at the place of study. An effort has already been started to realize
some of the designs in silicon and check their applicability in practical circuits. At the
basic level, one of the proposed Companding filter designs was implemented using the
commercially available transistor array ICs (LM3046N) and was found to verify the
theoretical predictions obtained from the simulation results
High Frequency Plasma Generators for Ion Thrusters
The results of a one year program to experimentally adapt two new types of high frequency plasma generators to Argon ion thrusters and to analytically study a third high frequency source concept are presented. Conventional 30 cm two grid ion extraction was utilized or proposed for all three sources. The two plasma generating methods selected for experimental study were a radio frequency induction (RFI) source, operating at about 1 MHz, and an electron cyclotron heated (ECH) plasma source operating at about 5 GHz. Both sources utilize multi-linecusp permanent magnet configurations for plasma confinement. The plasma characteristics, plasma loading of the rf antenna, and the rf frequency dependence of source efficiency and antenna circuit efficiency are described for the RFI Multi-cusp source. In a series of tests of this source at Lewis Research Center, minimum discharge losses of 220+/-10 eV/ion were obtained with propellant utilization of .45 at a beam current of 3 amperes. Possible improvement modifications are discussed
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