Time-based control techniques for integrated DC-DC conversion

Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or Gm-C integrators while a delay line is used to perform voltage-to-time conversion and to sum time signals. A simple flip-flop generates a pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for a wide bandwidth error amplifier, pulse width modulator (PWM) in analog controllers or high-resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in a small area and with minimal power. First, a time-based single-phase buck converter is proposed and fabricated in a 180nm CMOS process, the prototype buck converter occupies an active area of 0.24mm^2, of which the controller occupies only 0.0375mm^2. It operates over a wide range of switching frequencies (10-25 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V with 1.8V input voltage. With a 500mA step in the load current, the settling time is less than 3.5us and the measured reference tracking bandwidth is about 1MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2uA/MHz. Second, the techniques are extended to a high switching frequency multi-phase buck converter. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high-resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32mm^2, of which the controller occupies only 0.04mm^2. The converter operates over a wide range of switching frequencies (30-70 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V from 1.8V input voltage. With a 400mA step in the load current, the settling time is less than 0.6us and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3uA/MHz. Finally, light load operation is discussed. The light load efficiency of a time-based buck converter is improved by adding proposed PFM control. At the same time, the proposed seamless transition techniques provide a freedom to change the control mode between PFM and PWM without deteriorating output voltage which allows for a system to manage its power efficiently. Fabricated in a 65nm CMOS, the prototype achieves 90% peak efficiency and > 80% efficiency over an ILOAD range of 2mA to 800mA. VO changes by less than 40mV during PWM to PFM transitions

On-chip Voltage Regulator– Circuit Design and Automation

Title from PDF of title page viewed May 24, 2021Dissertation advisors: Masud H Chowdhury and Yugyung LeeVitaIncludes bibliographical references (page 106-121)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2021With the increase of density and complexity of high-performance integrated circuits and systems, including many-core chips and system-on-chip (SoC), it is becoming difficult to meet the power delivery and regulation requirements with off-chip regulators. The off-chip regulators become a less attractive choice because of the higher overheads and complexity imposed by the additional wires, pins, and pads. The increased I2R loss makes it challenging to maintain the integrity of different voltage domains under a lower supply voltage environment in the smaller technology nodes. Fully integrated on-chip voltage regulators have proven to be an effective solution to mitigate power delivery and integrity issues. Two types of regulators are considered as most promising for on-chip implementation: (i) the low-drop-out (LDO) regulator and (ii) the switched-capacitor (SC)regulator. The first part of our research mainly focused on the LDO regulator. Inspired by the recent surge of interest for cap-less voltage regulators, we presented two fully on-chip external capacitor-less low-dropout voltage regulator design. The second part of this proposal explores the complexity of designing each block of the regulator/analog circuit and proposed a design methodology for analog circuit synthesis using simulation and learning-based approach. As the complexity is increasing day-by-day in an analog circuit, hierarchical flow mostly uses for design automation. In this work, we focused mainly on Circuit-level, one of the significant steps in the flow. We presented a novel, efficient circuit synthesis flow based on simulation and learning-based optimization methods. The proposed methodology has two phases: the learning phase and the evaluation phase. Random forest, a supervised learning is used to reduce the sample points in the design space and iteration number during the learning phase. Additionally, symmetric constraints are used further to reduce the iteration number during the sizing process. We introduced a three-step circuit synthesis flow to automate the analog circuit design. We used H-spice as a simulation tool during the evaluation phase of the proposed methodology. The three most common analog circuits are chosen: single-stage differential amplifier, operational transconductance amplifier, and two-stage differential amplifier to verify the algorithm. The tool is developed in Python, and the technology we used is0.6um. We also verified the optimized result in Cadence Virtuoso.Introduction -- On-chip power delivery system -- Fundamentals of on-chip voltage regulator -- LDO design in 45NM technology -- LDO design in technology -- Analog design automation -- Proposed analog design methodology -- Energy efficient FDSOI and FINFET based power gating circuit using data retention transistor -- Conclusion and future wor

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks

Low Power DC-DC Converters and a Low Quiescent Power High PSRR Class-D Audio Amplifier

High-performance DC-DC voltage converters and high-efficient class-D audio amplifiers are required to extend battery life and reduce cost in portable electronics. This dissertation focuses on new system architectures and design techniques to reduce area and minimize quiescent power while achieving high performance. Experimental results from prototype circuits to verify theory are shown. Firstly, basics on low drop-out (LDO) voltage regulators are provided. Demand for system-on-chip solutions has increased the interest in LDO voltage regulators that do not require a bulky off-chip capacitor to achieve stability, also called capacitor- less LDO (CL-LDO) regulators. Several architectures have been proposed; however, comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This dissertation compares CL-LDOs in a unified manner. Five CL-LDO regulator topologies were designed, fabricated, and tested under common design conditions. Secondly, fundamentals on DC-DC buck converters are presented and area reduction techniques for the external output filter, power stage, and compensator are proposed. A fully integrated buck converter using standard CMOS technology is presented. The external output filter has been fully-integrated by increasing the switching frequency up to 45 MHz. Moreover, a monolithic single-input dual-output buck converter is proposed. This architecture implements only three switches instead of the four switches used in conventional solutions, thus potentially reducing area in the power stage through proper design of the power switches. Lastly, a monolithic PWM voltage mode buck converter with compact Type-III compensation is proposed. This compensation scheme employs a combination of Gm-RC and Active-RC techniques to reduce the area of the compensator, while maintaining low quiescent power consumption and fast transient response. The proposed compensator reduces area by more than 45% when compared to an equivalent conventional Type-III compensator. Finally, basics on class-D audio amplifiers are presented and a clock-free current controlled class-D audio amplifier using integral sliding mode control is proposed. The proposed amplifier achieves up to 82 dB of power supply rejection ratio and a total harmonic distortion plus noise as low as 0.02%. The IC prototype’s controller consumes 30% less power than those featured in recently published works

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Microelectronic Design with Integrated Magnetic and Piezoelectric Structures

This thesis investigates the possibility of integrating the standard CMOS design process with additional microstructures enhancing circuit functionalities. More specifically, the thesis faces the problem of miniaturization of magnetic and piezoelectric devices mostly focused on the application field of EH (Energy Harvesting) systems and ultra-low power and ultra-low voltage systems. It shows all the most critical aspects which have to be taken into account during the design process of miniaturized inductors for PwrSoC (Power System on Chip) or transformers. Furthermore it shows that it is possible to optimize the inductance value and also performances by means of a proper choice of the size of the planar core or choosing a different layout shape such as a serpentine shape in place of the classic toroidal one. A new formula for the correct evaluation of the MPL (Magnetic Path Length) was also introduced. Concerning the piezoelectric counterpart, it is focused on the design and simulation of various MEMS PTs based on a SOI (Silicon on Insulator) structure with AlN (Alluminum Nitride) as active piezoelectric element, in perspective of having a SoC with embedded MEMS devices and circuitry. Furthermore it demonstrates for the first time the use of a PT (Piezoelectric Transformer) for ultra-low voltage EH applications. A new boost oscillator based on a discrete PZT (Lead Zirconate Titanate) PT instead of a MT (Magnetic Transformer) has been modelled and tested on a circuit made up by discrete devices, showing performances comparable to commercial solutions like the LTC3108 from Linear. Furthermore this novel boost oscillator has been designed in a 0.35μm technology by ST Microelectronics, showing better performances as intuitively expected by the developed mathematical model of the entire system

CMOS Integrated Power Amplifiers for RF Reconfigurable and Digital Transmitters

abstract: This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below: 1) A transformer-based power combiner architecture for out-phasing transmitters 2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA) 3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB. The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%. Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201