An Optimized Switching Strategy Based on Gate Drivers with Variable Voltage to Improve the Switching Performance of SiC MOSFET Modules

This paper proposes an optimized switching strategy (OSS) based on a silicon carbide (SiC) MOSFET gate driver with variable voltage, which allows simultaneous variations in several different parameters to optimize the switching performance of semiconductor devices. As a relatively new device, the SiC MOSFET shines in the field of high power density and high-frequency switching; it has become a popular solution for electric vehicles and renewable energy conversion systems. However, the increase in voltage and current slope caused by high switching speeds inevitably increases the overshoot and oscillation in a circuit and can even generate additional losses. The principle of this new control strategy is to change the voltage and current in the turn-on and turn-off stages by changing the gate driver’s voltage. That is, we reduced the drive’s voltage after a certain time delay and maintained it for a period of time, thus directly controlling the slopes of di/dt and dv/dt. This study focused on the optimization of the SiC MOSFET by changing the time delay preceding the decrease in the voltage of the gate driver, analyzing and calculating the optimal time delay before the decrease in the voltage of the gate driver, and verifying the findings using LTspice simulation software. The simulated results were compared and analyzed with hard-switching strategies. The results showed that the proposed OSS can improve the switching performance of SiC MOSFETs

Parameters Design and Optimization of SiC MOSFET Driving Circuit with Consideration of Comprehensive Loss and Voltage Stress

In conventional parameters design, the driving circuit is usually simplified as an RLC second-order circuit, and the switching characteristics are optimized by selecting parameters, but the influence of switching characteristics on the driving circuit is not considered. In this paper, the insight mechanism for the gate-source voltage changed by overshoot and ringing caused by the high switching speed of SiC MOSFET is highlighted, and we propose an optimized design method to obtain optimal parameters of the SiC MOSFET driving circuit with consideration of parasitic parameters. Based on the double-pulse circuit, we evaluated the influence of main parameters on the gate-source voltage, including driving voltage, driving resistance, gate parasitic inductance, and stray inductance of the power circuit. A SiC-based boost PFC is constructed and tested. The test results show that the switching loss can be reduced by 7.282 W by using the proposed parameter optimization method, and the over-voltage stress of SiC MOSFET is avoided

Evaluation and Suppression Method of Turn-off Current Spike for SiC/Si Hybrid Switch

SiC MOSFET/Si IGBT (SiC/Si) hybrid switch usually selects the gate control pattern that SiC MOSFET turns on earlier and turns off later than Si IGBT, with the aim of making the hybrid switch show excellent switching characteristics of SiC MOSFET and reduce switching loss. However, when SiC MOSFET turns off, the fast slew rate of drain source voltage causes the current spike in Si IGBT due to the effects of parasitic capacitance charging and carrier recombination, which will produce additional turn-off loss, thus affecting the overall efficiency and temperature rise of the converter. Based on the double pulse test circuit of SiC/Si hybrid switch, the mathematical model of the turn-off transient process is established. The effects of the remnant carrier recombination degree of Si IGBT, the turn-off speed of SiC MOSFET and the working conditions on the turn-off current spike of hybrid switch are evaluated. Although adjusting these parameters can reduce the turn-off current spike somewhat, additional losses will be introduced. Therefore, a new method to suppress the turn-off current spike is proposed to balance the power loss and current stress

A novel active gate driver for improving SiC MOSFET switching trajectory

The trend in power electronic applications is to reach higher power density and higher efficiency. Currently, the wide band-gap devices such as silicon carbide MOSFET (SiC MOSFET) are of great interest because they can work at higher switching frequency with low losses. The increase of the switching speed in power devices leads to high power density systems. However, this can generate problems such as overshoots, oscillations, additional losses, and electromagnetic interference (EMI). In this paper, a novel active gate driver (AGD) for improving the SiC MOSFET switching trajectory with high performance is presented. The AGD is an open-loop control system and its principle is based on gate energy decrease with a gate resistance increment during the Miller plateau effect on gate-source voltage. The proposed AGD has been designed and validated through experimental tests for high-frequency operation. Moreover, an EMI discussion and a performance analysis were realized for the AGD. The results show that the AGD can reduce the overshoots, oscillations, and losses without compromising the EMI. In addition, the AGD can control the turn-on and turn-off transitions separately, and it is suitable for working with asymmetrical supplies required by SiC MOSFETs.Postprint (author's final draft

Design and Implementation of High-Efficiency, Lightweight, System-Friendly Solid-State Circuit Breaker

Direct current (DC) distribution system has shown potential over the alternative current (AC) distribution system in some application scenarios, e.g., electrified transportation, renewable energy, data center, etc. Because of the fast response speed, DC solid-state circuit breaker (SSCB) becomes a promising technology for the future power electronics intensive DC energy system with fault-tolerant capability. First, a thorough literature survey is performed to review the DC-SSCB technology. The key components for DC-SSCB, including power semiconductors, topologies, energy absorption units, and fault detection circuits, are studied. It is observed that the prior studies mainly focus on the basic interruption capability of the DC-SSCB. There are not so many studies on SSCB’s size optimization or system-friendly functions. Second, an insulated gate bipolar transistor (IGBT) based lightweight SSCB is proposed. With the reduced gate voltage, the proposed SSCB can limit the peak fault current without the bulky and heavy fault current limiting the inductor, which exists in the conventional SSCB circuit. Thus, the specific power density of the SSCB is substantially improved compared with the conventional design. Meanwhile, to understand the impact of different design parameters on the performance of SSCB, an analytical model is built to establish the relationship between SSCB dynamic performance and operating conditions considering the key components and circuit parasitics. Simulation and test results demonstrate the accuracy of the proposed model. To limit the fault current with the proposed SSCB without a current limiting inductor, power semiconductors need to operate in the active region temporarily. During this interval, a severe voltage oscillation has been observed experimentally, leading to the DC-SSCB overstress and eventually the failure. A detailed MATLAB/Simulink model is built to understand the mechanism causing the voltage oscillation. Three suppression methods using enhanced gate drive circuitry are proposed and compared. Test results based on a 2kV/1kA SSCB prototype demonstrate the effectiveness of the proposed oscillation mitigation method and the accuracy of the derived model. Meanwhile, when the system fault impedance is close to zero (e.g., high di/dt), the influence of the parasitic inductance contributed by interconnection (e.g., bus bar, module package, etc.) cannot be neglected. To study the influence of the bus bar connections on SSCB with high di/dt, a Q3D extractor is adopted to extract the parasitic parameters of the SSCB and understand the influence of different bus bar connections. A vertical bus bar is proposed to suppress the side effect and verified by the Q3D extractor and experimental results. Finally, a system-friendly SSCB is demonstrated. The proposed gate drive enables the SSCB to operate in the current limitation mode for the overcurrent limitation. The current limitation level and limitation time can be tuned by the gate drive. Then, this dissertation provides an all-in-one solution with integrated circuitries as the fault detector, actuator for the semiconductor’s operating status regulation, and coordinated control. This allows the developed SSCB to limit system fault current not exceeding short-circuit current rating (SCCR) and also take different responses under different fault cases. The feasibility and the effectiveness of the proposed system-friendly SSCB are validated with experimental results based on a 200V/10A SSCB demonstrator

Modeling, Measurement and Mitigation of Fast Switching Issues in Voltage Source Inverters

Wide-bandgap devices are enjoying wider adoption across the power electronics industry for their superior properties and the resulting opportunities for higher efficiency and power density. However, various issues arise due to the faster switching speed, including switching transient voltage overshoot, unstable oscillation, gate driving and evaluation difficulty, measurement and monitoring challenge, and potential load insulation degradation. This dissertation first sets out to model and understand the switching transient voltage overshoots. Unique oscillation patterns and features of the turn-on and turn-off overvoltage are discovered and analyzed, which provides new insights into the switching transient. During the experimental characterization, a new unstable oscillation pattern is found during the trench MOSFET\u27s turn-off transient. The MOSFET channel may be falsely turned back on, resulting in severe oscillation and possible loss of control. Time-domain and large-signal analytical models are established, which reveals the negative impact of common-source inductances and unconventional capacitance curve of trench MOSFET. Besides the devices themselves, another determining part in their switching transient behavior is the gate driver. A programmable gate driver platform is proposed to readily adapt to different power semiconductors and driving schemes, which can greatly facilitate the evaluation and comparison of different devices and driving schemes. The faster switching speed of wide-bandgap devices also requires more demanding measurement and monitoring solutions. A novel combinational Rogowski coil concept is proposed, which leverages the self-integrating feature to further increase the bandwidth. Prototypes achieved more than 300 MHz bandwidth, while keeping the cross-sectional area less than 2.5 mm$^2$. Finally, the very high voltage slew rate of wide-bandgap devices may negatively impact the motor load insulation. Attempting to fully utilize the higher switching frequency capability, sinewave and $dv/dt$ filters are compared. It is shown that sinewave filters can achieve higher efficiency and power density than $dv/dt$ filters, especially for high frequency applications

MMC with parallel-connected MOSFETs as an alternative to wide bandgap converters for LVDC distribution networks

LVDC networks offer improved conductor utilisation on existing infrastructure and reduced conversion stages, which can lead to a simpler and more efficient distribution network. However, LVDC networks must continue to support AC loads, requiring efficient, low distortion DC-AC converters. In addition, there are increasing numbers of DC loads on the LVAC network requiring controlled, low distortion, unity power factor AC-DC converters with increasing capacity, and bi-directional capability. An efficient AC-DC/DC-AC converter design is therefore proposed in this paper to minimise conversion loss and maximise power quality. A comparative analysis is carried out for a conventional IGBT 2-level converter, a SiC MOSFET 2-level converter, a Si MOSFET MMC and a GaN HEMT MMC, in terms of power loss, reliability, fault tolerance, converter cost, and heatsink size. The analysis indicates that the 5-level MMC with parallel-connected Si MOSFETs is an efficient, cost effective converter for LV converter applications. MMC converters suffer negligible switching loss, which enables reduced device switching without loss penalty from increased harmonics and filtering. Optimal extent of parallel connection for MOSFETs in an MMC is investigated. Experimental results are presented for current sharing in parallel-connected MOSFETs, showing reduction in device stress and EMI generating transients through the use of reduced switching

Gate Drive Design for Paralleled SiC MOSFETs in High Power Voltage Source Converters

High power voltage source converters (VSC) are vital in applications ranging from industrial motor drives to renewable energy systems and electrified transportation. In order to achieve high power the semiconductor devices used in a VSC need to be paralleled, making the gate drive design complicated. The silicon carbide (SiC) MOSFET brings much benefit over similarly rated silicon (Si) devices but further complicates the gate drive design in a parallel environment due to it’s fast switching capability and limited short-circuit withstand time. A gate driver design with proper accommodation of key issues for paralleled 1.7 kV SiC MOSFETs in high power VSC applications is developed.Three of the main issues are current imbalance, short-circuit protection, and cross-talk. By characterizing devices and supporting circuitry an understanding of constraints and sensitivities with regards to current balance between devices is developed for design optimization. A short-circuit detection scheme with adequate response time is employed and mitigation steps presented for issues arising from paralleling devices including large transient energy and instability. Cdv/dt induced gate voltage—cross-talk—is addressed by adapting a mitigation method to multiple devices. Finally, the gate driver is demonstrated in a full scale half-bridge using four devices per switch