New Hardware Architecture for Low-Cost Functional Test Systems Applications to HDMI generation

English: Development of a new test hardware architecture for functional test systems. Development of a proof-of-concept prototype for HDMI generation.Castellano: Desarrollo de una nueva arquitectura para equipos de test destinados a máquinas de test funcional de PCBs. Desarrollo de un prototipo de demostración destinado a la generación de HDMI.Català: Desenvolupament d'una nova arquitectura per equips de test destinats a màquines de test funcional de PCB. Desenvolupament d'un prototip de demostració destinat a generació d'HDM

Miniaturized GPS/MEMS IMU integrated board

This invention documents the efforts on the research and development of a miniaturized GPS/MEMS IMU integrated navigation system. A miniaturized GPS/MEMS IMU integrated navigation system is presented; Laser Dynamic Range Imager (LDRI) based alignment algorithm for space applications is discussed. Two navigation cameras are also included to measure the range and range rate which can be integrated into the GPS/MEMS IMU system to enhance the navigation solution

저 잡음 디지털 위상동기루프의 합성

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 정덕균.As a device scaling proceeds, Charge Pump PLL has been confronted by many design challenges. Especially, a leakage current in loop filter and reduced dynamic range due to a lower operating voltage make it difficult to adopt a conventional analog PLL architecture for a highly scaled technology. To solve these issues, All Digital PLL (ADPLL) has been widely studied recently. ADPLL mitigates a filter leakage and a reduced dynamic range issues by replacing the analog circuits with digital ones. However, it is still difficult to get a low jitter under low supply voltage. In this thesis, we propose a dual loop architecture to achieve a low jitter even with a low supply voltage. And bottom-up based multi-step TDC and DCO are proposed to meet both fine resolution and wide operation range. In the aspect of design methodology, ADPLL has relied on a full custom design method although ADPLL is fully described in HDL (Hardware Description Language). We propose a new cell based layout technique to automatically synthesize the whole circuit and layout. The test chip has no linearity degradation although it is fully synthesized using a commercially available auto P&R tool. We has implemented an all digital pixel clock generator using the proposed dual loop architecture and the cell based layout technique. The entire circuit is automatically synthesized using 28nm CMOS technology. And s-domain linear model is utilized to optimize the jitter of the dual-loop PLL. Test chip occupies 0.032mm2, and achieves a 15ps_rms integrated jitter although it has extremely low input reference clock of 100 kHz. The whole circuit operates at 1.0V and consumes only 3.1mW.Abstract i Lists of Figures vii Lists of Tables xiii 1. Introduction 1 1.1 Thesis Motivation and Organization 1 1.1.1 Motivation 1 1.1.2 Thesis Organization 2 1.2 PLL Design Issues in Scaled CMOS Technology 3 1.2.1 Low Supply Voltage 4 1.2.2 High Leakage Current 6 1.2.3 Device Reliability: NBTI, HCI, TDDB, EM 8 1.2.4 Mismatch due to Proximity Effects: WPE, STI 11 1.3 Overview of Clock Synthesizers 14 1.3.1 Dual Voltage Charge Pump PLL 14 1.3.2 DLL Based Edge Combining Clock Multiplier 16 1.3.3 Recirculation DLL 17 1.3.4 Reference Injected PLL 18 1.3.5 All Digital PLL 19 1.3.6 Flying Adder Clock Synthesizer 20 1.3.7 Dual Loop Hybrid PLL 21 1.3.8 Comparisons 23 2. Tutorial of ADPLL Design 25 2.1 Introduction 25 2.1.1 Motivation for a pure digital 25 2.1.2 Conversion to digital domain 26 2.2 Functional Blocks 26 2.2.1 TDC, and PFD/Charge Pump 26 2.2.2 Digital Loop Filter and Analog R/C Loop Filter 29 2.2.3 DCO and VCO 34 2.2.4 S-domain Model of the Whole Loop 34 2.2.5 ADPLL Loop Design Flow 36 2.3 S-domain Noise Model 41 2.3.1 Noise Transfer Functions 41 2.3.2 Quantization Noise due to Limited TDC Resolution 45 2.3.3 Quantization Noise due to Divider ΔΣ Noise 46 2.3.4 Quantization Noise due to Limited DCO Resolution 47 2.3.5 Quantization Noise due to DCO ΔΣ Dithering 48 2.3.6 Random Noise of DCO and Input Clock 50 2.3.7 Over-all Phase Noise 50 3. Synthesizable All Digital Pixel Clock PLL Design 53 3.1 Overview 53 3.1.1 Introduction of Pixel Clock PLL 53 3.1.1 Design Specifications 55 3.2 Proposed Architecture 60 3.2.1 All Digital Dual Loop PLL 60 3.2.2 2-step controlled TDC 61 3.2.3 3-step controlled DCO 64 3.2.4 Digital Loop Filter 76 3.3 S-domain Noise Model 78 3.4 Loop Parameter Optimization Based on the s-domain Model 85 3.5 RTL and Gate Level Circuit Design 88 3.5.1 Overview of the design flow 88 3.5.2 Behavioral Simulation and Gate level synthesis 89 3.5.1 Preventing a meta-stability 90 3.5.1 Reusable Coding Style 92 3.6 Layout Synthesis 94 3.6.1 Auto P&R 94 3.6.2 Design of Unit Cells 97 3.6.3 Linearity Degradation in Synthesized TDC 98 3.6.4 Linearity Degradation in Synthesized DCO 106 3.7 Experiment Results 109 3.7.1 DCO measurement 109 3.7.2 PLL measurement 113 3.8 Conclusions 117 A. Device Technology Scaling Trends 118 A.1. Motivation for Technology Scaling 118 A.2. Constant Field Scaling 120 A.3. Quasi Constant Voltage Scaling 123 A.4. Device Technology Trends in Real World 124 B. Spice Simulation Tip for a DCO 137 C. Phase Noise to Jitter Conversion 141 Bibliography 144 초록 151Docto

High-Speed Wide-Field Time-Correlated Single-Photon Counting Fluorescence Lifetime Imaging Microscopy

Fluorescence microscopy is a powerful imaging technique used in the biological sciences to identify labeled components of a sample with specificity. This is usually accomplished through labeling with fluorescent dyes, isolating these dyes by their spectral signatures with optical filters, and recording the intensity of the fluorescent response. Although these techniques are widely used, fluorescence intensity images can be negatively affected by a variety of factors that impact the fluorescence intensity. Fluorescence lifetime imaging microscopy (FLIM) is an imaging technique that is relatively immune to intensity fluctuations and also provides the unique ability to directly monitor the microenvironment surrounding a fluorophore. Despite the benefits associated with FLIM, the applications to which it is applied are fairly limited due to long image acquisition times and high cost of traditional hardware. Recent advances in complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diodes (SPADs) have enabled the design of low-cost imaging arrays that are capable of recording lifetime images with acquisition times greater than one order of magnitude faster than existing systems. However, these SPAD arrays have yet to realize the full potential of the technology due to limitations in their ability to handle the vast amount of data generated during the commonly used time-correlated single-photon counting (TCSPC) lifetime imaging technique. This thesis presents the design, implementation, characterization, and demonstration of a high speed FLIM imaging system. The components of this design include a CMOS imager chip in a standard 0.13 μm technology containing a custom CMOS SPAD, a 64-by-64 array of these SPADs, pixel control circuitry, independent time-to-digital converters (TDCs), a FLIM specific datapath, and high bandwidth output buffers. In addition to the CMOS imaging array, a complete system was designed and implemented using a printed circuit board (PCB) for capturing data from the imager, creating histograms for the photon arrival data using field-programmable gate arrays, and transferring the data to a computer using a cabled PCIe interface. Finally, software is used to communicate between the imaging system and a computer.The dark count rate of the SPAD was measured to be only 231 Hz at room temperature while maintaining a photon detection probability of up to 30\%. TDCs included on the array have a 62.5 ps resolution and a 64 ns range, which is suitable for measuring the lifetime of most biological fluorophores. Additionally, the on-chip datapath was designed to handle continuous data transfers at rates capable of supporting TCSPC-based lifetime imaging at 100 frames per second. The system level implementation also provides sufficient data throughput for transferring up to 750 frames per second from the imaging system to a computer. The lifetime imaging system was characterized using standard techniques for evaluating SPAD performance and an electrical delay signal for measuring the TDC performance. This thesis concludes with a demonstration of TCSPC-FLIM imaging at 100 frames per second -- the fastest 64-by-64 TCSPC FLIM that has been demonstrated. This system overcomes some of the limitations of existing FLIM systems and has the potential to enable new application domains in dynamic FLIM imaging

New techniques in television to provide research in three-dimensional real-time or near real-time imagery and reduced cost systems for teleconferencing and educational uses, part 1

The results are presented of a continuing research and development program the objective of which is to develop a reduced bandwidth television system and a technique for television transmission of holograms. The result of the former is a variable frame rate television system, the operation of which was demonstrated for both black-and-white and color signals. This system employs a novel combination of the inexpensive mass storage capacity of a magnetic disc with the reliability of a digital system for time expansion and compression. Also reported are the results of a theoretical analysis and preliminary feasibility experiment of an innovative system for television transmission of holograms using relatively conventional TV equipment along with a phase modulated reference wave for production of the original interference pattern

SIMD based multicore processor for image and video processing

制度:新 ; 報告番号:甲3602号 ; 学位の種類:博士(工学) ; 授与年月日:2012/3/15 ; 早大学位記番号:新595

A novel parallel algorithm for surface editing and its FPGA implementation

A thesis submitted to the University of Bedfordshire in partial fulfilment of the requirements for the degree of Doctor of PhilosophySurface modelling and editing is one of important subjects in computer graphics. Decades of research in computer graphics has been carried out on both low-level, hardware-related algorithms and high-level, abstract software. Success of computer graphics has been seen in many application areas, such as multimedia, visualisation, virtual reality and the Internet. However, the hardware realisation of OpenGL architecture based on FPGA (field programmable gate array) is beyond the scope of most of computer graphics researches. It is an uncultivated research area where the OpenGL pipeline, from hardware through the whole embedded system (ES) up to applications, is implemented in an FPGA chip. This research proposes a hybrid approach to investigating both software and hardware methods. It aims at bridging the gap between methods of software and hardware, and enhancing the overall performance for computer graphics. It consists of four parts, the construction of an FPGA-based ES, Mesa-OpenGL implementation for FPGA-based ESs, parallel processing, and a novel algorithm for surface modelling and editing. The FPGA-based ES is built up. In addition to the Nios II soft processor and DDR SDRAM memory, it consists of the LCD display device, frame buffers, video pipeline, and algorithm-specified module to support the graphics processing. Since there is no implementation of OpenGL ES available for FPGA-based ESs, a specific OpenGL implementation based on Mesa is carried out. Because of the limited FPGA resources, the implementation adopts the fixed-point arithmetic, which can offer faster computing and lower storage than the floating point arithmetic, and the accuracy satisfying the needs of 3D rendering. Moreover, the implementation includes Bézier-spline curve and surface algorithms to support surface modelling and editing. The pipelined parallelism and co-processors are used to accelerate graphics processing in this research. These two parallelism methods extend the traditional computation parallelism in fine-grained parallel tasks in the FPGA-base ESs. The novel algorithm for surface modelling and editing, called Progressive and Mixing Algorithm (PAMA), is proposed and implemented on FPGA-based ES’s. Compared with two main surface editing methods, subdivision and deformation, the PAMA can eliminate the large storage requirement and computing cost of intermediated processes. With four independent shape parameters, the PAMA can be used to model and edit freely the shape of an open or closed surface that keeps globally the zero-order geometric continuity. The PAMA can be applied independently not only FPGA-based ESs but also other platforms. With the parallel processing, small size, and low costs of computing, storage and power, the FPGA-based ES provides an effective hybrid solution to surface modelling and editing

Advanced Modulation and Coding Technology Conference

The objectives, approach, and status of all current LeRC-sponsored industry contracts and university grants are presented. The following topics are covered: (1) the LeRC Space Communications Program, and Advanced Modulation and Coding Projects; (2) the status of four contracts for development of proof-of-concept modems; (3) modulation and coding work done under three university grants, two small business innovation research contracts, and two demonstration model hardware development contracts; and (4) technology needs and opportunities for future missions